Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies

Abstract

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

1. Introduction

Due to its outstanding properties, silicon carbide (SiC) is an excellent candidate for replacing conventional silicon-based power devices, especially for applications operating in harsh environments [1]. SiC MOSFETs offer a superior dynamic and thermal performance compared to traditional Silicon (Si) power MOSFETs. One key advantage of SiC as substrate material is that the achievable electric fields are around ten times higher than for their Si counterparts, which allows the design of MOSFETs with smaller on-resistance and smaller parasitic capacitance.

The features mentioned above for SiC MOSFETs have a positive impact, for instance, on the power dissipation for either lower or higher power levels [2] and play an essential role in the field of robust microelectronic devices. However, the performance of SiC MOSFETs is still below the theoretical limit of SiC, mainly due to the trapping of electrons in the channel region. Even though post-oxidation annealing has enabled the fabrication of high-quality SiC power transistors, the devices still suffer from a considerable number of imperfections at the semiconductor/insulator interface. The trapping of charge carriers at such defect states gives rise to a notable drift of the threshold voltage of SiC transistors, which is known as the bias temperature instability (BTI) [3,4]. As a consequence of BTI, an increase of $V_{\mathrm{th}}$ during the operation of the device introduces additional delays in circuits.

Furthermore, this may also lead to a higher on-resistance which negatively affects the power conversion efficiency of selected circuits [3]. Thus, the reliability of circuits employing SiC devices needs to be studied very carefully, especially for applications where the stable device performance and the lifetime are critical [5]. A particular challenge for high-power devices is that the drift of the threshold voltage in return can lead to an increase of the losses in the transistor and cause and increase in the operating temperature of the system [6]. Thus, threshold voltage stability is an essential issue for power devices and applications. To optimize the performance and analyze the circuit behavior under certain operating conditions, circuit simulations employing Spice simulators are a beneficial tool. In Spice simulators accurate compact models are the key components to precisely reproduce the electrical behavior of either devices or circuits. In our work we employ both physical device simulations and circuit simulations to evaluate the behavior of logic inverter circuits using different device technologies.

In more detail, we make use of 2nd and 3rd generation of commercially available SiC power MOSFETs provided by Cree, specifically the devices are C2M0280120D and C3M0065090J, respectively. All device kinds are fabricated on SiC substrate, however, their behavior it terms of drift of the threshold voltage is different. This is due to the fact that each device has been fabricated under different processing conditions which leads to a different trap distribution. As a consequence, our reliability model has to be calibrated to each device variant, i.e., to each device technology, individually. In the following we will refer to C3M0065090J as T1 and C2M0280120D as T2 to better comprehend the results. We also used the SCT10N120 SiC power MOSFET from STMicroelectronics. Likewise, we will identify this device from now on as T3. The device vendors provide the respective spice models of the transistors [7,8], which we employ in our simulations. The models have been calibrated using static and dynamic measurements. However, these models typically do not account for aging mechanisms such as BTI. To close this gap, we evaluate the impact of BTI on the device behavior under operation, e.g., the drift of the threshold voltage over time. Furthermore, we combine the provided models with our calibrated reliability simulations to thoroughly analyze the degradation of the performance of the inverter circuits over time.

2. Charge Trapping and Model Calibration

One of the most prominent stability issues of devices is the so -called BTI. This aging mechanism has been extensively studied in the literature for Si/SiO₂ [9,10,11,12], Si/HK [13,14,15,16] and SiC/SiO₂ material systems [17]. BTI typically evolves as a drift of the threshold voltage with operation time and is characterized at higher gate voltages to accelerate $∆V_{\mathrm{th}}$ degradation. The origin of the observed $∆V_{\mathrm{th}}$ lies in charge trapping at interface traps and oxide defects [18,19].

Using measure-stress-measure (MSM) experiments [18], one can study this phenomenon as well as the creation of new defects. Typically power-law functions have been widely used to reproduce the threshold voltage drift $∆V_{\mathrm{th}}$ with stress time. However, using power-law-like formulas can lead to an erroneous prediction of BTI’s impact on the device and circuit parameters. This simple formula does not account for the saturation of $∆V_{\mathrm{th}}$ at high-stress times [19]. To ensure full accuracy in simulations, physical charge trapping models, for instance, the two-state defect model represented in Figure 1, should be preferably used [20,21]. This model is implemented in our open-source reliability simulator Comphy [21]. Our BTI simulator Comphy employs a two-state defect model based on the non-radiative multiphonon (NMP) theory. Moreover, it is used to calculate the charge capture and emission events at oxide defects to explain the $∆V_{\mathrm{th}}$. The most important parameters, as well as the expressions to determine the charge transitions times ${\tau }_{\mathrm{c}}$ and ${\tau }_{\mathrm{e}}$, are shown in the configuration coordinate diagram in Figure 1. The principle idea of the model is that a charge carrier has to overcome the energy barrier depicted as $E_{12}$ and $E_{21}$ to change the charge state of a certain defect. In the semi-classical picture the barriers can be computed considering the intersection of the parabolas. Their relative position of the parabolas thereby depends on the applied gate bias and the energetic trap level of the defect. $E_2$ refers to the energy level of the carrier reservoir (e.g., conduction band edge or valence band edge), and $E_1$ describes the trap level of the defect. Other model parameters are the curvature of the parabolas c, the electron concentration n, the thermal velocity $v_{\mathrm{th},\mathrm{n}}$, the capture cross-section $\sigma$, and the tunneling coefficient $\nu$.

Using Comphy the experimental data from various transistor technologies can be accurately reproduced. In [17,19] we make use of this model to precisely explain charge trapping at DC and AC operating conditions, as shown in Figure 2, for the technologies investigated in this work. It has to be noted that especially the saturation of the threshold voltage drift behavior can be nicely explained by this model [19].

The calibration of our reliability simulation tool is based on two types of experiments [19,22]: (i) DC-MSM sequences for different bias applied at room temperature, see Figure 3 (left), and (ii) AC-MSM measurements to characterize the operation of the transistors in switching applications, see Figure 3 (right). In the last case, a short AC stress during a time around 100 ms is applied repeatedly. At the last AC cycle of the signal, the stress is interrupted ($t_{\mathrm{AC},\mathrm{interrupt}}$). Then a $∆V_{\mathrm{th}}$ recovery trace is extracted for a time equal to 10 ms considering a fixed $I_{\mathrm{D}}$ = 1 mA through the channel of the device.

To ensure full accuracy of our simulation framework the tools are calibrated considering both DC and short-term AC experimental data to derive the surface potential from a given gate voltage, doping concentration in the channel, the oxide thickness and work function difference for each technology. As can be seen in Figure 4, Figure 5 and Figure 6, using our theoretical model can nicely replicate the device behavior for static and quasi-static operation conditions. This enables us now to look more detailed into the impact of BTI on different circuits.

3. Compact Modeling of BTI for Circuit Simulations

As has been previously discussed, with the compact models provided for circuit simulations, the static device behavior can be nicely reproduced. However, such models do not account for time-dependent changes in the device characteristics. To consider the impact of BTI on the transistors using spice simulations, we have to extend the model by adding an independent voltage source to the gate of the transistors. This additional voltage source accounts for the threshold voltage drift, $∆V_{\mathrm{th}}$ [23], and the schematic of the modified model is depicted in Figure 7.

Since the transistors are typically used in switching applications, transient circuit simulations are carried out next. For this purpose, we perform AC simulations employing ngspice and combine them with calculations made using our reliability tool for accounting the $∆V_{\mathrm{th}}$. The additional voltage source connected to the gate of the transistor contains the variability/degradation effects predicted employing the physical defect trapping model [24] implemented in the reliability simulator Comphy [21].

With each simulation, considering the accurate $∆V_{\mathrm{th}}$ values, it is possible to demonstrate that an overestimation of the $∆V_{\mathrm{th}}$ extracted values using power-law-like functions. Likewise, this difference in the $∆V_{\mathrm{th}}$ can lead to a very pessimistic prediction of inverter circuits parameters such as the propagation delay time $t_{\mathrm{D}}$.

In Figure 8, the simulation process flow using the open-source ngspice simulator is illustrated. To perform our reliability simulations, we define the net-list of the circuit based on the spice models of the respective SiC power MOSFETs (step 1). Next, an external file contains the $∆V_{\mathrm{th}}$ values extracted from Comphy (step 2) for a long operation time (ten years). This file is used to modify the initial net-list of the circuit. Then we extract the aged parameters of the circuit for a specific degradation and time point, taking into account the principle shown in Figure 7 (step 3). Note that such simulations can become easily computationally demanding. The simulation time depends on the number of $∆V_{\mathrm{th}}$ values in the external file. The ngspice simulator launches a new simulation every time that the initial net-list is modified. However, this net-list modification does not significantly increase the simulation time. As a result of the circuit simulations, we obtain the aged circuit parameters at extended operation time considering the impact of BTI on the SiC MOSFETs. We can process these results to analyze the plots of the aged electrical characteristics of the device (step 4).

4. Results and Discussion

The first circuit we evaluate is the typical resistivity load inverter, see Figure 9 (left). With this circuit, we can efficiently verify our approach and implementation to determine the BTI impact in the propagation delay $t_{\mathrm{D}}$ considering only one transistor. The values are extracted as the time difference when $V_{\mathrm{in}}$ and $V_{\mathrm{out}}$ are equal to $V_{\mathrm{DD}}$/2, as we show in Figure 9 (right). Each value of the delay time distribution $t_{\mathrm{D}}$ represents the aging of the inverter circuit for each $∆V_{\mathrm{th}}$ or, equivalently, for a certain degradation of the device with time.

In Figure 10 shows the $∆V_{\mathrm{th}}$ values extracted after ten years ($\approx {10}^8$ s) of operational time considering an AC input signal with a typical switching frequency for SiC applications equal to $f_{\mathrm{SW}}$ = 50 kHz, duty cycle of 50%, $V_{\mathrm{High}}=20 \mathrm{V}$ and $V_{\mathrm{Low}}=0 \mathrm{V}$. The time of the zero voltage in the input signal ensures the recovery phase for the $∆V_{\mathrm{th}}$ extraction. Likewise, we consider the case for $V_{\mathrm{High}}=V_{\mathrm{Low}}$ = 20 V (DC stress) to compare the $∆V_{\mathrm{th}}$ values extracted when the recovery phase is omitted. For all devices the $∆V_{\mathrm{th}}$ values are presented in the same plot for a long-term DC and short-term AC stress sequences to highlight the differences obtained between Comphy simulations with and without recovery. As can be seen, the latter leads to a significant overestimation of the $∆V_{\mathrm{th}}$.

As can be seen, the threshold voltage of the transistors drifts around 0.3–0.9 V after ten years of operation if the recovery phase is considered. Almost five times more, between 1.5–6 V, if the recovery phase is omitted. The propagation delay time for the resistivity load inverter circuit based on the different commercial SiC transistors T1, T2, and T3, considering the $∆V_{\mathrm{th}}$ extracted values, are presented in Figure 11. These results represent the BTI impact on the simple test inverter circuit considering only the degradation of one transistor independently for a long operating time. Considering $∆V_{\mathrm{th}}$ = 0 (fresh simulations), the extracted propagation delay time for the three technologies was 39 ns, 78 ns, and 169 ns for T1, T2, and T3, respectively. An increase of the threshold voltage drift over time also causes an increase in the propagation delay time of the inverter circuit. In all the cases, the increase of the propagation delay time $∆t_{\mathrm{D}}$ is expressed in (%) and represents the difference between the $t_{\mathrm{D}}$ for a specific operating time ($∆V_{\mathrm{th}}\ne 0$) and the initial value ($∆V_{\mathrm{th}}$ = 0). After ten years of operating time $t_{\mathrm{D}}$ increases up to 41 ns, 85 ns, and 172 ns, for T1, T2, and T3, respectively. From these results, we can note that the increase of the propagation delay time is similar (between 2–4 ns) for each technology. However, the BTI impact (computed as an increase of the propagation delay time, see Figure 11) on T1/T2 technologies (8%) is more significant than for T3 (1.5%). One possible explanation for this is due the propagation delay time is one order higher for T3 technology. Finally, our results also show that when the recovery phase is omitted, the $t_{\mathrm{D}}$ is overestimated for all technologies.

The following circuit we analyze is the pseudo-D CMOS inverter. In literature, this circuit is proposed for thin-film transistors [25,26] to implement inverters employing mono-type transistors. We make use of our simulation approach and extract the $t_{\mathrm{D}}$ for a pseudo-D CMOS inverter circuit, shown in Figure 12, designed with mono-type transistors [27]. For the analysis of this circuit, it is essential to mention that we only use the T1 device. Considering that these devices were fabricated for only one channel width and length, it was impossible to design this inverter with T2 and T3 due to impedance coupling. However, thanks to the Kelvin Source pin architecture (which allows more voltage applied between the gate and source, resulting in a faster dynamic switching and reduction of the inductive effects at the gate of the device), it was possible to design and simulate the pseudo-D CMOS inverter circuit using the T1 device.

For this circuit, we compute the total degradation by evaluating $∆V_{\mathrm{th}}$ of each transistor individually at each simulation time step. Figure 13 shows the $t_{\mathrm{D}}$ distribution values for ten years of operation considering the degradation of all transistors at the same time and the degradation of each transistor individually. An overestimation of the propagation delay of the pseudo-D logic inverter circuit for a long operation time can be observed. The propagation delay $t_{\mathrm{D}}$ is a few nanoseconds larger when the recovery phase of the AC signal is omitted for each transistor. This can lead to challenges for circuits operating at higher frequencies. Note that this difference in the predicted delay does not arise from real devices, but rather is a consequence of the inaccuracy of simple models. The results for N2 and N4 show a similar impact on $t_{\mathrm{D}}$. On the other hand, for N1 and N3, the circuit seems to be practically insensitive to BTI.

5. Conclusions

For a highly accurate description of the behavior of aging circuits, physical device models are required for circuit simulations. However, existing approaches use compact models that are typically based on simple mathematical formulas for circuit analysis and cannot account for aging mechanisms such as BTI at a very high accuracy over a wide range of temperature, bias and operating conditions. In our work, we combine our transistor reliability simulator Comphy with circuit simulations made using ngspice. We employ three transistor technologies and extend the compact models provided by the device vendors to be suitable for precise BTI evaluation. After Comphy is calibrated to extensive DC and AC measurements, we evaluate the propagation delay of the inverter circuits. Specifically, we analyze the resistivity load inverter circuit and the pseudo-D-CMOS inverter based on the same three different technologies, T1, T2, and T3. Our results show that the BTI has a more significant impact on T1/T2 technology than T3. On the other hand, the same results demonstrate that employing simple power-law-like formulas leads to an overestimation of the signal propagation delay, leading to severe challenges during circuit design. We also demonstrate that omitting device recovery during the low-phase under AC operation leads to a considerable overestimation of the signal propagation delay of the circuits.