FPGA Verification for the OR1200 Subsystem in AVS-SoC

Abstract:

This paper adopts a completely open-source OR1200 to development the CPU subsystem in AVS-SoC video decoder. Through the reasonable optimization and configuration for the core and its peripherals, it greatly enhanced the AVS chip’s reusability and integration level. At first, the author successfully completed the simulation in RTL-level. And then for the OR1200 can be better used in AVS video decoder chip, designers set up a verification platform for OR1200 subsystem on FPGA board. The author elaborated on the process of software design and hardware transplant from ASIC to FPGA, and then verified and optimized the performance for this CPU subsystem. Setting up AVS decoding system on FPGA, the project can software/hardware co-verify the video decoder, which will greatly accelerate the SoC chip’s development. Through the verification on FPGA board, testing for OR1200-based system has achieved the desired results.