Design Methodology of the Class-E Power Amplifier with Finite Feed Inductance—A Tutorial Approach

Abstract

The Class-E with finite feed inductance is a high-efficiency power amplifier that generally uses complex, long, and iterative design procedures. In this paper, we detail a design methodology that is based on an analytical model of this amplifier. This methodology explores the power amplifier design by the use of a symbolic mathematical tool, which was developed in the software Maple™. This approach helps to understand the Class-E circuit topology and it offers a fast and easy design procedure without having to examine, in-depth, the model analytical equations.

1. Introduction

The Class-E power amplifier is a tuned switching Power Amplifier (PA), which is commonly used in Radio-Frequency (RF) applications. It uses a single switch element and a tuned reactive network between its power stage and its load. Furthermore, it achieves an ideal power efficiency of 100% under Zero Voltage Switching (ZVS) and Zero Voltage Derivative Switching (ZVDS) conditions. The circuit topology and its main waveforms are shown in Figure 1 and Figure 2, respectively. This PA is used in many applications, such as wireless power transmission [1], dedicated short-range communications [2], low-power RF devices [3], induction heater systems [4], plasma generators [5], and street-lighting [6].

The Class-E amplifier was introduced by Ewing in 1964, as a high-efficiency RF amplifier [7]. Since then, this PA has been analyzed in several works [8,9,10,11,12,13,14,15,16,17,18,19,20,21]. In contrast to the original implementation with RF choke inductors for Direct Current (DC) feeding, the use of a finite inductance offers a higher degree of freedom, a feature that is particularly useful in applications with size constraints, because it allows for the reduction of the inductor size [16]. For instance, in [19], the authors design a Class-E with Finite DC Feed Inductance (FDI) that is based on an integrated split inductor. Additionally, their design involves the breakdown limit of the integrated switch as a design restriction and it maximizes the PA output power under ZVS and ZVDS conditions while using an analytical model of the Class-E PA with FDI. Furthermore, to the best of our knowledge , the use of this topology has been concentrated only on applications in which the conventional topology (i.e., with RF choke) cannot be implemented (e.g., VLSI and RF applications).

In general, the Class-E with FDI models are more complex than the Class-E conventional models [15]. In particular, the conventional models assumed the feed current as a DC current that results in simple analytical equations [7], while in the Class-E with FDI models considered the current behavior into the circuit analysis [17]. Furthermore, some published models set the duty cycle (D) of the commutation signal to a fixed value (e.g., 0.5), which simplifies the amplifier model and design equations [12,15]. Following another simplification approaches , in [17,18], the authors assumed a high loaded quality factor and ideal components (i.e., ideal switch, inductors, and capacitors with infinite quality factor) to model the Class-E with FDI through analytical equations, which allows for an easy design procedure with mathematical software tools. However, the designer needs to implement the PA model in a software tool without some insight into its analytical equations expressed as explicit functions of the model variables and without a detailed procedure for obtaining these equations, because they were not reported in [17,18]. Only after overcoming this challenge, the designer could optimize the Class-E with FDI to a particular application by an exhaustive exploration of the design space when considering the involved trade-offs between the design specifications and restrictions [19].

The design of the Class-E PA with FDI has been explored in several works [11,12,16,17,18,19,20,22,23,24,25]. In general, the complexity of the circuit design of the Class-E with FDI is higher than the calculation of conventional Class-E components in order to guarantee ZVS and ZVDS operation. This design process involves multivariable equations with high complexity solutions which could require iterative procedures to achieve the given specifications and restrictions [13,15,16,17,18,19,20,25,26,27]. In [11,12,13], the authors design a Class-E with FDI using an iterative design approach, which involves time-consuming procedures. On one hand, these procedures usually involve a phase of tuning components to achieve the ZVS and ZVDS conditions [21,28,29]. On the other hand, other models, like the ones proposed in [17,18], provide accurate analytic equations, which avoid iterative solutions with lower accuracy predictions under high values of parasitic elements of the amplifier components. The model that is presented in [17] considers two design parameters, which are D and the resonance frequency mismatch (q). The model proposed in [18] considers three design parameters: D, q, and the normalized slope of the switch voltage (S). The S parameter allows for defining three operation modes: non-ZVS, suboptimal operation (i.e., ZVS and non-ZVDS), and optimal operation (i.e., ZVS and ZVDS).

Commonly, the design equations synthesized from these analytical models are summarized into a set of math expressions that establish a link between circuit components and input parameters, these expressions are called the PA design set [17,18,19]. Under the amplifier optimal operation, the design set proposed by [17,18,19] is the same, and it allows the calculation of a large number of possible combinations of the circuit parameters, which guarantee the ZVS and ZVDS operation of the ideal Class-E with FDI under the specifications and restrictions of the particular application. However, this set is not widely used perhaps, because the model implementation demands extensive mathematical development, and to the best knowledge of the authors, a systematic methodology to explore the freedom of this analytical model is not reported, in particular with the possibility to analyze the design space when considering the involved trade-offs between design specifications and restrictions.

This paper proposes a novel design methodology of the Class-E with FDI based on the analytical model that was proposed by [17,19]. Furthermore, to simplify its adoption by the academic and scientific community, we share the PA model implementation, and the code used to apply the proposed method. In addition, this paper has been written following a tutorial approach to motivate related engineers and students with basic knowledge in circuit theory in order to integrate these amplifiers in their projects by following this paper (and its additional material) as a practical handbook. We devote particular attention to the selected examples to present the impact of the proposed methodology to optimize the PA. The outline of this paper is as follows. Section 2 presents the Class-E PA modeling and design equations. Section 3 describes the design methodology and explains two design approaches. Section 4 shows four design study cases. Finally, in Section 5 and Section 6, the conclusions and the future work are presented.

2. PA Model and Design Set

2.1. PA Model

The Class-E is a power amplifier that reduces the switching losses by turning on the switch with zero voltage and zero current in the $C_{SH}$ capacitor (i.e., ZVS and ZVDS operation), as illustrated in Figure 2c,f, respectively. This PA is fed by a DC source ($V_{DD}$) and a pulsed source ($v_g$) with a fundamental frequency $f_o$. Furthermore, it supplies the power that is delivered to its load ($R_L$) in a narrow band centered in $f_o$ while using a quasi-tuned LC circuit, where the natural resonant frequency is

$${\omega }_e=\frac{1}{\sqrt{L_o{C}_e}}=\frac{1}{\sqrt{L_o{C}_o}}+\Delta \omega =2\pi f_o+\Delta \omega$$

(1)

where $\Delta \omega$ is the frequency offset necessary to guarantee the ZVS and ZVDS operation. In the ideal Class-E PA model, the quality factor of the storage elements is infinite. The switch has: zero on-resistance, infinite off-resistance, and zero rise and fall commutation times. Under these assumptions, and supposing a high value of $Q_L$, the Class-E PA with FDI circuit model could be simplified to the one that is shown in Figure 1b. The current $I_{R_L}$ is out of phase by an angle $\phi$ regarding the voltage $v_g$ (Figure 2d), and it is related to the load power ($P_{out}$) by

$$i_{RL}\left(t\right)=I_{p}sin(2\pi f_{o}t+\phi )=\sqrt{\frac{2P_{out}}{R_L}}sin({\omega }_{o}t+\phi ).$$

(2)

In the time intervals when the switch is on ($t_{on}$) and off ($t_{off}$), the main waveforms of the PA are predicted by the following equations [17,19]

$$\begin{array}{ccc}\hfill i_{C_{SHon}}\left(t\right)& =v_{C_{SHon}}\left(t\right)=0\hfill & \hfill \end{array}$$

(3)

$$\begin{array}{ccc}\hfill i_{S_{on}}\left(t\right)& =\frac{V_{DD}}{L_{SH}}t-I_{p}sin\left(\phi \right)+I_{p}sin({\omega }_{o}t+\phi )\hfill & \hfill \end{array}$$

(4)

$$\begin{array}{ccc}\hfill i_{L_{SHon}}\left(t\right)& =\frac{V_{DD}}{L_{SH}}t-I_{p}sin\left(\phi \right)\hfill & \hfill \end{array}$$

(5)

$$\begin{array}{ccc}\hfill i_{S_{off}}\left(t\right)& =0\hfill & \hfill \end{array}$$

(6)

$$\begin{array}{ccc}\hfill i_{L_{SHoff}}\left(t\right)& =\frac{V_{DD}}{L_{SH}}t-I_{p}sin\left(\phi \right)-\frac{1}{L_{SH}}{\int }_{\frac{2\pi D}{{\omega }_o}}^t{v}_{C_{SH}}d\tau \hfill & \hfill \end{array}$$

(7)

$$\begin{array}{ccc}\hfill i_{C_{SHoff}}\left(t\right)& =\frac{V_{DD}}{L_{SH}}t+I_p(sin({\omega }_{o}t+\phi )-sin\left(\phi \right))-\frac{1}{L_{SH}}{\int }_{\frac{2\pi D}{{\omega }_o}}^t{v}_{C_{SH}}d\tau \hfill & \hfill \end{array}$$

(8)

$$\begin{array}{ccc}\hfill v_{C_{SHoff}}\left(t\right)& =V_{DD}\left(\frac{C1}{V_{DD}}cos\left(q{\omega }_{o}t\right)+\frac{C2}{V_{DD}}sin\left(q{\omega }_{o}t\right)+1-\frac{q^2}{1-q^2}pcos({\omega }_{o}t+\phi )\right)\hfill & \hfill \end{array}$$

(9)

where

$$q=\frac{1}{{\omega }_o\sqrt{L_{SH}{C}_{SH}}}$$

(10)

$$D=\frac{t_{on}}{T}=t_{on}{f}_o$$

(11)

$$p=\frac{{\omega }_o{L}_{SH}}{V_{DD}/I_p}=\frac{{\omega }_o{L}_{SH}}{\sqrt{R_L·R_{DC}}}$$

(12)

The variable p is the ratio between the impedance of $L_{SH}$ at the operation frequency and the geometric mean of the resistance that the amplifier shows to the power supply ($R_{DC}$) and its load ($R_L$). The constants $C1$ and $C2$ are related to the solution of the involved differential equation. It is important to notice that the variable q cannot take the value of 1 because of the mathematical singularity that is introduced by (9). Furthermore, under ZVS and ZVDS conditions, $\phi$, p, $C1$, and $C2$ could be expressed as a function of D and q variables [17]

$$\phi =arctan\left(\frac{b_1{c}_2-b_2{c}_1}{\pm \sqrt{{(a_1{c}_2-a_2{c}_1)}^2+{(b_1{c}_2-b_2{c}_1)}^2}},\frac{a_1{c}_2-a_2{c}_1}{\pm \sqrt{{(a_1{c}_2-a_2{c}_1)}^2+{(b_1{c}_2-b_2{c}_1)}^2}}\right)$$

(13)

$$p=\frac{\pm \sqrt{{(a_1{c}_2-a_2{c}_1)}^2+{(b_1{c}_2-b_2{c}_1)}^2}}{a_2{b}_1-a_1{b}_2}$$

(14)

$$C1=p{V}_{DD}\left(\frac{q^2}{1-q^2}cos\left(2q\pi \right)cos\left(\phi \right)+\frac{q}{1-q^2}sin\left(2q\pi \right)sin\left(\phi \right)\right)-V_{DD}cos\left(2q\pi \right)$$

(15)

$$C2=p{V}_{DD}\left(\frac{q^2}{1-q^2}sin\left(2q\pi \right)cos\left(\phi \right)-\frac{q}{1-q^2}cos\left(2q\pi \right)sin\left(\phi \right)\right)-V_{DD}sin\left(2q\pi \right)$$

(16)

where

$$a_1=1-\frac{1}{q^2-1}cos\left(q2\pi \right(D-1\left)\right)+\frac{q^2}{q^2-1}cos\left(2\pi D\right)$$

(17)

$$b_1=-\frac{1}{q^2-1}sin\left(q2\pi \right(D-1\left)\right)-\frac{q^2}{q^2-1}sin\left(2\pi D\right)$$

(18)

$$c_1=2\pi D-\frac{1}{q}sin\left(q2\pi \right(D-1\left)\right)$$

(19)

$$a_2=\frac{q}{q^2-1}sin\left(q2\pi \right(D-1\left)\right)-\frac{q^2}{q^2-1}sin\left(2\pi D\right)$$

(20)

$$b_2=-\frac{q}{q^2-1}cos\left(2\pi D\right)-\frac{q^2}{q^2-1}cos\left(q2\pi \right(D-1\left)\right)$$

(21)

$$c_2=1-cos\left(q2\pi \right(D-1\left)\right).$$

(22)

2.2. Design Set of the Ideal Class-E PA

Commonly, the conventional design set K of the ideal Class-E PA is composed of four equations (i.e., $K_P$, $K_L$, $K_C$, and $K_X$), which relate to the PA specifications and circuit components [7,17,23,30,31]. For instance, by fixing the specification values of $P_{out}$ and $V_{DD}$, the $K_P$ equation can be used to find the $R_L$ value through the expression that is shown in Figure 3. Therefore, in order to find the values of the circuit model from the design specifications, the expressions between the PA design variables (e.g., ${\omega }_o$, $R_L$, $C_{SH}$) that are shown in Figure 3 can be used. This design set is composed of analytical functions of the D and q variables, which are given by Equations (23)–(27) [17,19].

$$\begin{array}{cc}\hfill K_L& =\frac{{\omega }_o{L}_{SH}}{R_L}=\frac{p(D,q)}{2g_x(D,q)}\hfill \end{array}$$

(23)

$$\begin{array}{cc}\hfill K_C& ={\omega }_o{C}_{SH}{R}_L=\frac{2g_x(D,q)}{q^{2}p(D,q)}\hfill \end{array}$$

(24)

$$\begin{array}{cc}\hfill K_P& =\frac{P_{out}{R}_L}{V_{DD}^2}=2{\left(g_x(D,q)\right)}^2\hfill \end{array}$$

(25)

$$\begin{array}{cc}\hfill K_X& =\frac{X_s}{R_L}=\frac{\frac{1}{\pi }{\int }_0^{\frac{2\pi }{\omega }}\left(V_{C_{SH}}\left(t\right)cos(\omega t+\phi )\right)dt}{\frac{1}{\pi }{\int }_0^{\frac{2\pi }{\omega }}\left(V_{C_{SH}}\left(t\right)sin(\omega t+\phi )\right)dt}\hfill \end{array}$$

(26)

$$\begin{array}{cc}\hfill K_{Q_L}& =Q_L=\frac{{\omega }_o{L}_o}{R_L}=\frac{1}{{\omega }_o{C}_o{R}_L}\hfill \end{array}$$

(27)

where $X_s$ is a capacitive or inductive reactance that must be added to the resonant network (i.e., $L_o$ and $C_o$) to guarantee the ZVS and ZVDS operation. We add the $K_{Q_L}$ equation into the conventional design set, because the $Q_L$ defines the $L_o$ and $C_o$ values. The current gain of the PA under the small ripple approximation is given by [20]

$$g_x=\frac{{\langle i_s\left(t\right)\rangle }_{2\pi }}{I_p}=\left(\frac{1-cos\left(2\pi D\right)}{2\pi }\right)cos\left(\phi \right)+\left(\frac{sin\left(2\pi D\right)}{2\pi }-D\right)sin\left(\phi \right)+\frac{D^2\pi }{p}$$

(28)

where ${\langle x\rangle }_{2\pi }$ is the moving average operator over the $v_g$ period. The moving average of $i_s$ is given by [32]

$${\langle i_s\left(t\right)\rangle }_{2\pi }=\frac{{\omega }_o}{2\pi }{\int }_0^{\frac{2\pi D}{{\omega }_o}}{i}_s\left(\tau \right)d\tau .$$

(29)

In the design set that is composed of (23)–(27), the designer must fix the D and q values to design the PA from its specifications. In the literature, some “optimal” design equations have been proposed under particular restrictions.

Table 1. Design Sets of different Class-E PA models.

Parameter	Ewing [7] ${}^{\mathit{a}}$	Kazimierczuk [31]	Grebennikov [30]	Iwadare [23]	Acar [17] ${}^{\mathit{b}}$
$K_L$	∞	∞	0.732	3.534	0.732
$K_C$	0.184	0.184	0.685	0.071	0.685
$K_P$	0.577	0.577	1.365	0.056	1.365
$K_X$	0.637	1.152	0	-4.903	0
$R_{on}$ switch	finite	zero	zero	zero	zero
$L_{SH}$	infinite	infinite	finite	finite	finite
$C_{SH}$	linear	linear	linear	linear	linear
D	arbitrary	0.5	0.5	0.5	arbitrary

${}^a$ Calculated for D = 0.5 and zero on resistance. ${}^b$ Calculated for D = 0.5 and q = 1.412.

shows a summary of the selected proposals, which could be used in order to design the PA according to the application. The most common design set considers a duty cycle $D=0.5$ because it reduces the design complexity of the oscillator that controls the switch, and $q=1.412$ because it maximizes the load power for a fixed $V_{DD}$ and $R_L$ [17].

In a particular application, the PA designer can explore the design space defined by the D and q variables. On one hand, the design space of q was analyzed in [16] with a practical range between 0 and 1.9 for $D=0.5$. On the other hand, the design space of D was studied in [33,34], with a practical range between 0.25 and 0.75. Additionally, the maximum current and voltage values supported by the PA components can be analyzed into the design process as specifications. For example, in [19], the authors included the rupture voltage of the switch in the design process using the following equation [20]

$$V_{C_{SHm}}\approx \frac{1.7613+0.0500q}{1-D}{V}_{DD}.$$

(30)

As another example, in [35] the authors developed the analytical equation of the Root Mean Square (RMS) current thought the switch given by

$$I_{RM{S}_{SW}}=\frac{V_{DD}·g_x(D,q)}{R_L}\frac{f_1(D,q)}{f_2(D,q)}$$

(31)

where

$$\begin{array}{cc}\hfill f_1(D,q)=& 0.4532-0.348q+0.9159q^2+1.279D+1.344D^2-0.6721qD-1.589q^2{D}^2\hfill \\ \hfill & -0.1598q^3+0.7299D^3+1.039q^3{D}^3\hfill \end{array}$$

(32)

$$\begin{array}{cc}\hfill f_2(D,q)=& 3.615-7.482q+3.686q^2-7.518D+7.672D^2+19.41qD-11.87q^{2}D-15.74q{D}^2\hfill \\ \hfill & +9.707q^2{D}^2+0.1672q^3-0.6993D^3\hfill \end{array}$$

(33)

2.3. Maple™ Implementation of the Analytical PA Model and Its Design Set

This section briefly describes the Maple™ code used for implementing the analytical model and the design set of the Class-E PA with FDI presented in the previous subsections. This model is composed of the Equations (4)–(9) and the variables $\phi$, p, $C_1/V_{DD}$, $C_2/V_{DD}$, and $g_x$ expressed as explicit functions of the q and D variables. These last functions were found through the algebraic solution of the equations proposed in [17,19], and then they were coding in the Maple™ script presented in Appendix A.1. The amplifier design set was coded based on the implemented model, the solution of the Equation (26) (coded as an intermediate function $KX2$), and the functional operator feature of Maple™. The resulting script is described in Appendix A.2. As a result of this implementation approach, the amplifier model and its design set were coded as functions of the variables D and q. Finally, we code Equations (4)–(9) to estimate the main waveforms predicted by the model, the resulting script was summarized in Appendix A.3.

The scripts summarized in Appendix A could be used at least for two purposes. The first one is to plot the estimated waveforms under ZVS and ZVDS operation of the analytical model while using the D, $L_{SH}$, $C_{SH}$, $R_L$, and $V_{CC}$ values. The second one is to calculate the design set using the q and D values.

3. Design Methodology of the Ideal Class-E PA with FDI

The design flow of the proposed methodology is shown in Figure 4. In step 1, the designer defines the input parameters, the maximum ratings, and the optimization goals. The maximum ratings can be defined based on the manufacturer’s data sheets [19], the input parameters can be defined from the Class-E PA design specifications, and the optimization goals can be defined to maximize or minimize circuit variables (e.g., maximize the $P_{out}$). In steps 2 and 3, the designer must find the extended design set that involves the mathematical expressions for the unknown circuit values, maximum ratings, and optimization goals. In step 4, the designer must plot the search space (i.e., all possible values of the design variables subject to ZVS and ZVDS operation as a function of D and/or q) in a particular range of the D and q variables, if they are unknown. Once the designer explored the search space and found the optimum combination of D and q, the circuit components of the PA must be calculated in step 5, and the circuit operation must be verified in step 6. If all of the specifications are met, the design process is finalized. Otherwise, a new search of D or q values can be made to achieve it.

It is important to highlight that the design solution is an ideal approximation, which uses assumptions, such as ideal components. When the ZVS and ZVDS conditions are not achieved after the design implementation, either by the effect of non-ideal components or by approximation to commercial values, a tuning process can be performed. Commonly, this process fits the point of ZVS and ZVDS in order to accomplish the soft-switching operation by the tuning of the component values [21,28,29].

3.1. Design Approaches

In this subsection, we explore the design of an ideal Class-E with FDI for wireless transfer applications under two design approaches by applying the proposed methodology. These approaches are: to use an optimum value of D and q reported in the literature and to optimize the PA for minimizing the stress supported by the switch. These designs were calculated with Maple™ to simplify numerical development. These approaches were solved while using the support tools developed for this tutorial and the procedure reported in Appendix B. These tools could be used for different applications and design specifications with minor modifications. Furthermore, the validation of the design process was made by circuit simulations in OrCAD PSpice ^®Designer. All of the simulations employed transient analysis with a maximum time step of 1 ns, ideal components, voltage-controlled switch with zero fall and rise commutation times, off-resistance of 300 M$\Omega$, and on-resistance of 10 m$\Omega$.

3.1.1. Approach A: Design Based on a Reported Optimal Point

In this approach, the design specifications are based on the standard Qi™, which defines inductive charging guides for wireless power applications over short distances [36]. Following the design methodology that is proposed in Section 3, the design steps are:

Step 1: the specifications of the design were defined from the power class 0 specification of standard Qi™, which are summarized in

Table 2. Class-E PA specifications.

${\mathit{f}}_{\mathit{o}}$ [kHz]	${\mathit{V}}_{\mathbf{DD}}$ [V]	${\mathit{L}}_{\mathit{o}}$ [μH]	${\mathit{P}}_{\mathbf{in}}$ [W]	$\mathit{\eta }$	D	q
100	5	24	10	1	0.5	1.412

. The $L_o$ value corresponds to a commercial transmitter coil in compliance with the standard. The D and q values were defined in order to maximize the output power with low complexity of the switch driver [17]. Additionally, the only restriction considered was the breakdown voltage of the switch. Therefore, the $v_{C_{SHm}}$ value was limited to 30 V (typical maximum rating of MOSFETs for low voltage applications [37]).

Step 2: in this design, the unknown variables are $L_{SH}$, $C_{SH}$, $C_e$, and $R_L$. The process used to find these unknown values from the design set is illustrated in Figure 5. This diagram has four phases. In phase 1 is found the equation of $R_L$. In phase 2, are identified the expressions for calculating $C_{SH}$, $L_{SH}$, $X_s$, and $K_{Q_L}$. Subsequently, phase 3 identifies the expression of $C_o$, and finally, in phase 4 is found the $C_e$ equation. In the diagram shown in Figure 5, the input parameters or design specifications are shown in silver boxes, the relations of the design set in blue boxes, and the unknown expressions in white boxes. We followed this graphical notation in the diagrams that will appear in Section 4.

Step 3: the design set is extended by the expression of $V_{C_{SHm}}$ described in (30).

Step 4: this step is skipped, because D and q are specifications of this design.

Step 5: the extended design set was implemented in Maple™ while using the support tools developed for this tutorial. The resulting model parameters are listed in

Table 3. Model parameter values for approach A.

Parameter	Value *	Parameter	Value *	Parameter	Value *
$K_L$	0.7332	$K_X$	−0.0002	$C1/V_{DD}$	2.6106
$K_C$	0.6841	$\phi$	−2.4925	$C2/V_{DD}$	−2.1385
$K_P$	1.3632	p	43.8534	$g_x$	0.8256

* Calculated for D = 0.5 and q = 1.412.

, and the resulting circuit components and restrictions were listed in

Table 4. Circuit components and restriction values of approach A.

Variable	Design Values	Commercial Values
$R_L$ [$\Omega$]	3.41	3.40
$L_{SH}$ [$\mathsf{\mu }$H]	3.98	3.90
$C_{SH}$ [nF]	319.48	330.00
$C_e$ [nF]	105.54	100.00
$V_{C_{SHm}}$ [V]	18.32	NA
D	0.5	0.5
q	1.412	1.412

.

Step 6: in Figure 6, the theoretical (Model) and simulated (Ideal sim.) waveforms of the designed Class-E were plotted. These waveforms present ZVS and ZVDS operation under the design restriction of $V_{C_{SHm}}$ less than 30 V. Therefore, the simulation verifies the good performance of the designed Class-E PA.

The Class-E PA is susceptible to the component values. For instance, when the components found in the design process of the last example are approximated to the closest commercial component values, the simulated waveforms have significant changes (Comm. sim. in Figure 6). Furthermore, the ZVS and ZVDS conditions are not met and, consequently, the switch stress is increased. This electric stress could be quantified by the output power capability, which is given by [38]

$$C_p=\frac{P_{out}}{max\left\{V_p,V_{p_{on}}\right\}·max\left\{I_p,I_{p_{on}}\right\}}$$

(34)

where $I_p$ and $V_p$ are the peak current and peak voltage across the switch, respectively. The $I_{p_{on}}$ and $V_{p_{on}}$ are the current and voltage values at the switch turn-on time, as shown in Figure 7.

3.1.2. Approach B: Design under an Optimization Goal

In this approach, the Class-E PA is designed based on the same specifications of the approach A. However, we explore the overall PA design space in order to guarantee a high $C_p$ according to circuit values of commercial components.

Steps 1, 2, and 3: similar to the ones presented in Section 3.1.1. However, D and q are defined as design variables.

Step 4: the design search space was plotted in Figure 8. The variable D should be less than 0.625 to accomplish the design restriction (i.e., $V_{C_{SHm}}<30$ V), as shown in Figure 8a,b . An optimization process was developed over the search space of the components (Figure 8c–f in order to find circuit components under commercial values restriction. This process was implemented by parametric sweeps of the D and q variables. We plot, in Figure 8g, the sweep of the optimum D, from this family of curves we found the optimum value of q as $1.821$.

Step 5: following the process that is described in Section 3.1.1, we found the circuit components and its closest commercial values, as summarized in

Table 5. Circuit components and restriction values of approach B.

Variable	Design Values	Commercial Values
$R_L$ [$\Omega$]	3.95	3.90
$L_{SH}$ [$\mathsf{\mu }$H]	7.51	7.50
$C_{SH}$ [nF]	101.74	100.00
$C_e$ [nF]	102.36	100.00
$V_{C_{SHm}}$ [V]	24.37	NA
D	0.62	0.62
q	1.821	1.821

.

Step 6: the design was verified by simulation, obtaining satisfactory waveforms for the approximate commercial values, as shown in Figure 9 (comm. sim.).

Finally,

Table 6. Simulated circuit parameters.

Parameter	Approach A	Approach B	Optimization Effect * [%]
$V_p$ [V]	17.02	26.42	55.20
$V_{p_{on}}$ [V]	2.00	0.08	96.12
$I_p$ [A]	4.45	4.30	3.37
$I_{p_{on}}$ [A]	189.00	6.72	96.45
$P_{in}$ [W]	8.81	10.50	19.23
$P_{out}$ [W]	8.68	10.43	20.18
$\eta$	0.99	0.99	0.79
$C_p$	0.0027	0.0588	2078.94

* Optimization effect $=\frac{|ApproachA-ApproachB|}{ApproachA}·100$.

presents a comparison of the simulated results by following both design approaches with commercial components. The results are related to the electrical stress of the switch. The optimization process reduces the stress of the switch, in particular, the $C_p$ was increased by 2079% approximately.

3.2. Maple™ Implementation of Approach A and B

This section describes briefly the Maple™ script used to design the PAs with the approaches A and B of the proposed methodology. The script was divided into segments. In the first segment, the PA model variables and its design set were defined as a function of the D and q variables while using the script summarized in Appendix A.1 and Appendix A.2 (described in Section 2.3). In the next segment, the input parameters and extended design set were defined according to the results of steps 1 to 3 of the proposed methodology. Subsequently, if the variables D and/or q are unknown, then a dedicated segment plots the search space (3D or 2D), which are required in step 4 of the methodology. In the next segment, the script calculates the circuit components from the chosen values of D and q. In the last segment, the script plots the main circuit waveforms, which are used to compare the model estimation with the simulated values. This script was summarized in Appendix B, and it could be adapted with little modifications to the specific requirements of a particular application. For instance, we use a modified script in order to develop the amplifier designs that are reported in the next section. Additionally, as a support tool, we developed a basic code to start a new design following the proposed methodology (i.e., supplementary materials BasicCode.mw file in the support tools).

4. Study Cases and Analysis Results

In order to evaluate the proposed design methodology, four study cases were selected with the initial specifications listed in

Table 7. Design specifications.

Specification	Case 1	Case 2	Case 3	Case 4
D	0.4	0.5	nv	nv
q	nv	nv	nv	nv
$f_o$[MHz]	0.5	1	10	4
$Q_L$	nv	nv	30	32
$V_{DD}$[V]	12	nv	nv	6
$P_{in}$[W]	nv	1	8	6
$P_{out}$[W]	nv	1	8	6
$\eta$	1	1	1	1
$R_L[\Omega ]$	3.3	nv	2.4	nv
$L_o$[$\mathsf{\mu }$H]	nv	33	nv	nv
$C_e$[nF]	22	nv	nv	nv
$C_{SH}$[nF]	nv	22.6	nv	nv
maximize	$P_{out}$	$R_L$	$C_p$	$R_L$
$I_{RM{S}_{SW}}$	nv	nv	nv	<2A

nv: Unknown value.

. These cases show different design starting points and they involve the optimization of at least one circuit variable. In the first study case, the design goal is to find the maximum output power for a given $V_{DD}$ and $R_L$. This example could be useful in wireless power transfer applications, where the power amplifier load could be fixed into the PA design as a specification for maintaining the high efficiency of the inductive link while using an adaptive impedance matching network between the output of the amplifier and link [1,19]. The second case requires the maximum load resistance while using $D=0.5$. This design approach could be useful in VLSI applicationsm where the MOSFET driver is integrated, since, by setting D = 0.5, its layout complexity is reduced and consequently the overall chip size too [16]. Furthermore, maximizing the load value decreases the power dissipation in the parasitic elements of the output load network because the current delivered to the load under the same output power is decreased [19]. The design goal of the third study case is to find the maximum $C_p$ value for a given $P_{out}$, $R_L$, $f_o$, and $Q_L$. The $C_p$ maximization improves the useful life of the semiconductor device and reduces the cost of the amplifier; this feature is relevant for several Class-E applications. Finally, the fourth study case looks for the higher $R_L$ value with a limited RMS current through the switch. This design approach with a limited value of the switch RMS current could be used when the switch has size constraints, because the consumed power of the switch is directly related to this RMS value. Furthermore, the $R_L$ maximization could be used in order to reduce the losses in the quasi-tuned LC circuit, as we discussed before. In each case, the unknown circuit values were found applying the proposed methodology by using the software Maple™, the obtained solutions are listed in

Table 8. Design solutions.

Parameter	Case 1	Case 2	Case 3	Case 4
$R_L[\Omega ]$	3.30	4.94	2.40	10.90
$L_{SH}$[nH]	492.19	520.09	31.05	1.47
$C_{SH}$[nF]	133.02	22.60	2.60	172.20
$L_o$[$\mathsf{\mu }$H]	4.61	33.00	1.15	13.87
$C_e$[nF]	22.00	0.76	0.22	114.10
$V_{DD}$[V]	12.00	1.93	4.44	6.00
$P_{in}$[W]	50.28	1.00	8.00	6.00
$P_{out}$[W]	50.28	1.00	8.00	6.00
$\eta$	1	1	1	1
D	0.40	0.50	0.55	0.75
q	1.244	1.468	1.771	2.504
$Q_L$	4.39	41.94	30.00	32.00

. Additionally, the validation of the design solutions was made by circuit simulations in OrCAD PSpice ^®Designer software. In all simulations were used ideal components and a voltage-controlled switch with zero falls and rise commutation times, off-resistance of 300 M$\Omega$, and on-resistance of 10 m$\Omega$.

In study case 1, it is required the maximum output power for a given $V_{DD}$ and $R_L$, the specified duty cycle is 0.4, and the q value is undefined. The mathematical expressions of the unknown circuit values were obtained following the process that is described in the diagram of Figure 10. According to the $P_{out}$ search space plotted in Figure 11a, the maximum output power for $D=0.4$ is achieved at $q=$ 1.244. Therefore, the unknown circuit components were calculated and listed in Table 8 using $q=$ 1.244. Finally, the design solution was verified by simulation. The simulated $P_{out}$ was 50.82 W, and the waveforms of the output power and average output power are shown in Figure 11b.

In the second design, the maximum $R_L$ is found for a given $f_o$ and $C_{SH}$, the specified duty cycle is 0.5 and the q value is undefined. The expressions of unknown circuit components were obtained with the process that is shown in Figure 12. According to the $R_L$ search space plotted in Figure 13a, the maximum load resistance for $D=0.5$ is achieved at q = 1.468. Hence, the circuit parameters were calculated and summarized in Table 8 using $q=$ 1.468. Finally, the design solution was verified, the switch voltage and current obtained in the simulation are shown in Figure 13b, where a soft-switching behavior is observed.

In the study case 3, the maximum output power capability is found for a given $P_{out}$, $f_o$, $R_L$, where $Q_L$, the D and q values are undefined. The unknown circuit expressions were obtained following the process described in Figure 14. The $C_p$ variable search space is shown in Figure 15a, the curve behavior shows that the maximum $C_p$ is around $D=$ 0.5, and it decreases at extreme D values (i.e., $D=$ 0.25 and $D=$ 0.75). The maximum $C_p$ is achieved at $D=$ 0.55, for q = 1.771, as shown in Figure 15b. Therefore, the unknown parameters were calculated and are listed in Table 8 using these values. Finally, the design solution was verified. The simulated $C_p$ was 0.1071, the waveforms of the switch current and output power are shown in Figure 15c.

In the study case 4, the maximum $R_L$ value is found with the $I_{RM{S}_{SW}}$ being limited to 2 A, the D and q values are undefined. The expressions for the unknown circuit components were obtained with the process shown in Figure 16. The search space of $R_L$ and $I_{RM{S}_{SW}}$ are plotted as a function of D and q in Figure 17a,b, respectively. The analytical expression of $I_{RM{S}_{SW}}$ is taken from the Equation (31) . The curve behavior of Figure 17a shows that the $R_L$ value increases as D increases. Similarly, the curve behavior of Figure 17b shows that the $I_{RM{S}_{SW}}$ decreases as D increases. Consequently, the duty cycle is set at 0.75, because it allows a high $R_L$ value and restricts the RMS switch current under 2 A. According to Figure 17a, the maximum load resistance for $D=0.75$ is achieved at $q=$ 2.504. Therefore, the unknown parameters were calculated and are summarized in Table 8 while using $D=0.75$ and $q=$ 2.504. Finally, the design solution was verified by simulation, where the simulated switch RMS current was 1.39 A. The waveforms of the switch current and $I_{RM{S}_{SW}}$ are shown in Figure 17c. With D values different than 0.5, the q range to obtain the optimal solution can be greater than 1.9, as shown in Figure 17a.

The optimization goals and maximum ratings were verified in the simulation for each example, the obtained simulated results were summarized and confronted with the predicted values in

Table 9. Design results.

Study case	Parameter	Model	Simulated	APE *
1	$P_{in}$ [W]	50.28	51.36	2.14
	$P_{out}$ [W]	50.28	50.82	1.08
	$\eta$	1.00	0.99	1.04
2	$P_{in}$ [W]	1.00	1.00	0.13
	$P_{out}$ [W]	1.00	0.99	0.78
	$\eta$	1.00	0.99	0.65
3	$P_{in}$ [W]	8.00	8.95	11.89
	$P_{out}$ [W]	8.00	8.87	10.83
	$\eta$	1.00	0.99	0.95
	$C_p$	0.1082	0.10705	1.06
4	$P_{in}$ [W]	6.00	6.31	5.20
	$P_{out}$ [W]	6.00	6.28	4.69
	$\eta$	1.00	1.00	0.49
	$I_{RM{S}_{SW}}$ [A]	1.38	1.39	1.16

* APE $=\frac{|Model-Simulated|}{Model}·100$.

. The simulated efficiency in all cases was 0.99. The study cases 1 and 2 show a good performance, ZVS and ZVDS conditions are achieved, and the Absolute Percentage Error (APE) is less than 2.14% in the simulated parameters. In the third design, the predicted and simulated $C_p$ value has an absolute percentage error of 1.06%. The study case 4 accomplish an $R_L$ value 33% greater than the obtained with the typical operation point (the load resistance calculated with $D=$ 0.5 and $q=$ 1.412 is 8.18 $\Omega$ for the same specifications). Additionally, the $I_{RM{S}_{SW}}$ restriction is achieved and it has an APE of 1.16%. The Mean Absolute Percentage Error (MAPE) of the analyzed parameters is 3.01%, which verifies the adequate design procedure.

5. Conclusions

This paper presents a design methodology of the ideal Class-E PA with FDI, which explores the PA circuit components freedom easily by use of the mathematical software Maple™. The presented examples show the impact of the proposed methodology in PA optimization. Furthermore, a presentation and Maple™ codes were developed as support tools for this methodology proposal. We hope that this document and the support materials motivate engineers to integrate this amplifier into their projects.

6. Future Work

This paper presents the results of the first milestones reached under the framework of the research project entitled “Class E Amplifier with Gallium Nitride Transistors for Wireless Power Transfer Applications”, which aims to respond to the following research question: how to design a class E PA using transistors made of Gallium Nitride (GAN), ensuring high efficiency when the load is a standard inductive link for charging mobile phones? In future work, we will expand the proposed methodology with more analytical expressions that are related to the maximum rating constraints of the amplifier components, such as the RMS value of the feed inductance current. Furthermore, we will explore a specific tuning process to guarantee ZVS and ZVDS operation of the amplifier when its load is an inductive link and its switch is implemented by a CMOS or a GAN device.