Utilizing Parallel Superconducting Element as a Novel Approach of Flux-Coupled Type SFCL to Limit DC Current in the System

Abstract

To lessen the amount of energy lost during transmission, electricity is increasingly being sent using high-voltage lines. Transmission loss in a DC system is lower than in an AC system over long distances. The DC system can improve the efficiency of long-distance transmission by connecting power grids with different requirements. The DC method is becoming popular since it helps to keep the grid stable. Managing and blocking DC flow is crucial to system functionality. In this study, we explore the operation of a flux-coupled type superconducting fault current limiter (SFCL) in a DC system, where the two windings are connected in parallel to limit the fault current flow. A flux-coupled type SFCL is built by connecting two coils in parallel and a superconducting element (SE) in series with the secondary coil. The functions of an SFCL of the flux-coupled kind are equivalent in both direct and alternating current systems. Because of the opposing magnetic fluxes produced by the two coils, the voltage generated by the parallel connection of the coils is always zero. Inadequate SE leads to an increase in resistance, inhibiting the cancellation of opposing magnetic fluxes and hence a loss in power. Connecting the two coils in series allows voltage to be generated while the fault current is limited. To further validate the performance of SFCL with varying resistance and inductance, the system is additionally tested on the IEEE 39 bus system. The MATLAB/SIMULINK software suite is used to run the test system.

1. Introduction

High voltage is used to reduce transmission losses [1,2]. Compared with alternating current (AC), DC data transmission over long distances incurs less loss. The use of direct current (DC) to connect separate power grids can lessen the impact of transmission losses and increase the dependability of long-distance power transmission [2]. DC is gradually gaining popularity because it leads to a more reliable power grid. In DC systems, restricting and blocking DC is mandatory [3].

Direct current (DC) fault current must be rapidly handled to prevent harm to neighbouring systems [4]. It is essential that one of the defences (SFCL) is built out of a superconducting material [5]. The SFCL increases in speed when a superconducting material is quenched. Typically, an SFCL’s 0 R value means zero power loss [6]. When the fault current is interrupted by the SFCL’s superconducting component shaking [7], the SFCL is functioning as intended. Before an SFCL can be used in a real-world power system, more superconducting components are needed [8]. Because of this, SFCLs have been developed, and studies on SFCL triggers, double quench, and trans-formers have been conducted [9].

Installing an SFCL eliminates the requirement to switch off the main distribution board’s circuit breaker [10]. Therefore, it will likely significantly impact the economy [11]. It may be more cost effective to use an SFCL rather than to replace the circuit breaker. SFCL construction is underway in Europe [12] on transmission lines and in Japan [13] on distribution lines. SFCLs with 22.9 kV and 154 kV are now being built in South Korea [14].

Due to rising power consumption and generation, fault currents in power systems have expanded along with industrialization and economic development. The cost of replacing equivalent electrical equipment may increase as fault currents increase the breaking capacity of existing circuit breakers. A short circuit in the power system reduces voltage and disrupts the bus’s stability. The subject of research is the use of superconducting fault current limiters (SFCLs) to mitigate fault current in electrical networks [15].

Large SFCL capacities are not typically the most cost-effective choice, but they limit current more effectively than less expensive options. DC systems are difficult to block since there is no zero point. Arcing and blockage can be avoided if the fault current is limited to safe levels. Breakers are more reliable when SFCL is used to lower the fault current.

Every electrical grid relies on three primary components: power generation, transmission, and distribution. You can put limits on those three things by employing either SFCL or plain old FCL. It can be used if the fault current generation in the system becomes excessive. The voltages used by transmission lines are higher than those used by power plants and distribution networks. Despite the fact that some SFCL structures can be constructed for HV usage, it is anticipated that SFCL will be employed largely for low-voltage uses due to the insulating issue in HV applications.

The total cost of ownership (TCO), together with costs of development, maintenance, the recovery process, AC loss, volume, and weight, must be taken into account while making plans for or implementing SFCL. Several interesting new constructions have emerged in recent years. These include RSFCLs, HSFCLs, and SISFCLs. These SFCL models have been deployed to operational grids for continuous monitoring. In the long run, these SFCLs are likely to prove useful. Extensive testing has shown that SFCL has the potential to significantly lower fault currents in the presence of a real-world problem.

This research conducted short-circuit studies on a DC SFCL that gets one of its two triggering current levels from a transformer. To study DC SFCLs, a transformer was needed. The DC current limiting capabilities of CLR were investigated by conducting short-circuit tests on a transformer-based DC SFCL. This study contributes the following:

• Using an equivalency circuit analysis and a short circuit test, we studied an SFCL transformer with an extra-connected non-isolated circuit.
• SFCL performance was explored for I, V, and P. Peak cutting, quench sequence, and more for operation characteristics.
• In this paper, we investigate how a flux-coupled type superconducting fault current limiter (SFCL) with a parallel connection between two windings in a DC system controls fault current.
• The major goal of this strategy is that two coils will be connected in parallel, and a superconducting element (SE) will be connected in series with the secondary coil. Magnetic fluxes generated by each coil ensure that the voltage produced in the coil remains at zero even if the fault did not occur. The flux-coupled type SFCL has identical roles and responsibilities in DC systems as it does in AC systems.
• As a consequence of faults in the superconducting element, resistance builds up, which prevents magnetic fluxes from cancelling each other. In this way, the fault current is restricted by producing some voltages by both coils.
• To check the efficiency of the flux-coupled type SFCL, the IEEE 39 bus system is used for testing by using different values of resistance and inductance to check the system’s stability.
• In the test conditions, line-to-ground and three-phase fault are also studied. The injected voltages for specific intervals of line-to-ground and three-phase fault are provided to the system. SFCL restricts the voltage within the desired magnitude to make the load voltage constant. In this way, the system response is stable.

We investigate how a DC system’s fault current can be controlled using a flux-coupled superconducting fault current limiter (SFCL). There are two coils in parallel in a flux coupler SFCL, and the secondary coil has a superconducting element in series with it. RSC1 and RSC2 are linked together serially, while RSC1 and CLR are linked in parallel. Two superconducting elements are used in the DC SFCL to distribute the superconductor mass uniformly. A CLR reduces the amount of energy needed to keep a superconductor operating. RSC1 acts as a voltage divider when a fault current is present. It is through RSC1 and RSC2 that the fault current is gradually reduced. For this research, a robust IEEE 39 bus system was used to guarantee reliable operation. Together, capacitance and inductance affect the voltage, current, and power waveform. Over both a ground fault and a three-phase fault, we recorded significant voltage drops and spikes. By injecting a certain voltage during a sag/swell, a fault can be cleared and the load voltage stabilised. The results of contrasting the current study with the prior state of the art are shown in

Table 1. The comparative analysis of current study with previous state-of-the-art techniques.

References	Type of SFCL	Features	Drawbacks
[12]	RSFCL	Self-triggering, short response time, self-recovering (return to service without human intervention), fault current limitation, low normal voltage loss, and compact design.	AC loss, current leads, extended recovery time (typical type), high HTS in flux–flow type, and short limitation period.
[15]	Matrix RFCL	Rapid response, self-recovering, low voltage loss, and high voltage/current ratings.	AC loss, current leads, extended recovery time, short limitation period, high HTS, and high development cost.
[4]	HFCL	Rapid response, self-recovering, low voltage loss, and high voltage/current ratings.	Some potential topologies require AC loss (less than RSFCL), current leads, and a fault detection system.
[8]	Magnetic SFCL	Self-triggering, short response time, self-recovering (return to service without human intervention), fault current limitation, low normal voltage loss, and compact design.	High power loss and voltage drop in normal condition, long recovery time, huge and hefty size, iron core and non-conductive material for cryostat and insulations.
Proposed	FSFCL 39 Bus System	Rapid response, self-recovering, low voltage loss, and high voltage/current ratings. Quick detection and compensation in voltage sag/swell	Current and Instantanious power loss, Short limitations with extended recovery time, Fault detection and mitigation.

.

This paper has five sections. Section 1 is the introduction and context, Section 2 is a critical analysis of the literature, Section 3 is the research technique, Section 4 offers the results, and Section 5 provides conclusions.

2. Related Work

DC power transmission is gaining popularity as a high-efficiency alternative [1,2,3]. This is true in renewable energy transmission, HVDC, and DC microgrids. No natural zero crossing of fault current makes DC power system safety and dependability harder to assure. DCCBs are the best solution for fault prevention [4,5,6]. Figure 1 [7] shows a hybrid DCCB network topology.

Due to the quick increase in fault current and the DCCBs’ limited ultimate breaking capability, it is impossible to guarantee that protective systems will function in the case of a DC fault. So that DCCBs can successfully interrupt the fault current, the fault current must be limited [8]. Current-limiting inductors are frequently used in series with hybrid DCCB to reduce fault current [8,9]. Excessive inductance can slow down the responsiveness of a DC system and diminish its stability, while small inductance has a negligible effect on current. A resistive-type superconducting fault current limiter (R-SFCL) [10,11] is another practical method for limiting fault current in a DC system. In addition, the metal oxide arrester (MOA) is typically used to soak up any residual energy in the system following an interruption. However, there are some risks associated with arrester use, such as (1) internal partial discharge and (2) arresters falling apart forcibly under excessive weights [12].

As an alternative to these more traditional forms of protection, superconducting fault current limiters (SFCLs) can be used since they have no resistance during normal-current operation, suffer no loss during fault-current faults, and do not need any extra fault detection or operational circuitry. This is why several different SFCL concepts and schemes have been presented and technically proven over the course of the last few decades [11,12,13], typically for use in power transmission and distribution networks. There are numerous common varieties, such as the saturated core [14], transformer [15], reactor [16], flux lock [17], magnetic shield [18], resistive [19,20], and many more.

Multiple high-voltage, high-capacity SFCL prototypes have been developed and deployed into real-world power grid environments in the past few years. In China, demonstrations of high-voltage SFCL projects have been carried out on grids with voltages ranging from 220 to 500 kilovolts of alternating current (AC) [21], 500 to 160 kilovolts of direct current (DC) [22], and 160 kilovolts of AC [23]. Due to the technical requirements of external grids and the quenching safety concerns of the SFCL, the nominal lasting period for the fault current suppression is often restricted to a few seconds [11,12,13,14,15,16,17,18,19,20,21,22,23]. In light of this, it appears that SFCLs’ primary function is to quickly and effectively alleviate the effects of transient fault current. Scientists have recently looked towards sophisticated hybrid systems based on SFCL and other power system protection technologies to further boost system security during grid outages. A failure in a high-voltage direct-current (HVDC) system, for instance, can be stopped with the use of a DC circuit breaker and SFCL [24]. Fault current is mitigated by the SFCL, and power to the damaged wire is quickly shut off by the DC circuit breaker.

Energy storage and an SFCL can be used in a flexible DC system powered by renewable sources to smooth out voltage swings under normal conditions and limit current spikes in the case of a malfunction [25,26]. Few studies have looked at the self-acting protection of power electronic equipment and DC-DC converters utilising a low-cost SFCL device for their applications in renewable-based microgrids (fault durations are generally from hundreds to thousands of milliseconds; [27,28,29]). Contrary to what is found in system-level analyses [30,31], power electronic switches and devices can be seriously harmed by errors that last only milliseconds.

This has made the question of how to swiftly and reliably protect power electrical switches and devices from failure increasingly pressing in recent years. The subject of how to promptly and safely reduce the over current that results from faults and disturbances in DC-to-DC converters and DC microgrids is of crucial importance.

This study proposes employing a small SFCL for fail-safe DC-to-DC conversions as a means of avoiding the time-delay, self-malfunction, and mis-judgment problems that afflict conventional power electronic devices and systems. Unlike traditional overcurrent limiting methods, which rely on hardware and software, the SFCL is totally based on the current-dependent resistance of the superconducting materials. Our research and simulations verify the newly built SFCL’s self-acting over-current limiting and terminal voltage-stabilizing capabilities, which are useful for analysing DC-to-DC converters and delving deeper into the DC microgrid.

3. Methodology

In Figure 2, we see a flowchart illustrating the application of SFCL analysis to the problem of resolving unsymmetrical faults in a power system.

To further enhance line voltage stabilisation, closed-loop control methods may be implemented in DC-DC converters, and duty ratios may be adjusted in power switch circuits. The SFCLSMES combo strategy has the ability to rapidly reduce fault current and stabilise line voltage by making use of superconducting magnetic energy storage technology.

In Figure 3, we can see the SFCL control loop, where E represents the disparity between y c and the actual output

$$E=y_c-y$$

(1)

where y is the output of the system and $G$ is the transfer function and u is the updated value after calculating the error as:

$$y=G.u=G.E$$

(2)

Replacing Error E is the equation, it becomes:

$$y=G.(y_c-y)$$

(3)

$$y=G.y_c-G.y$$

(4)

$$\frac{y}{y_c}=\frac{G}{1+G}$$

(5)

3.1. Modelling SFCL

During the negative and positive cycles, SFCL’s two iron cores are saturated with high DC current from a superconducting winding supply. Losses can be neglected if a direct current (DC) is employed in the superconducting winding. The normal and faulty alternating currents travel through two typical metal windings that are linked in series to the power line (one wound on each core). The following (Figure 4) is a schematic diagram showing the electrical configuration at SFCL:

Since the DC current is so much higher than the AC current, the two iron cores are saturated in both directions under normal working conditions. This is why they have such low values of magnetic permeability and inductance. Each cycle’s midpoint is marked by an increase in alternating current (AC) to counteract the DC current, and the emergence of one iron core from the saturation zone.

Saturated-core SFCL can reduce fault current because it increases magnetic permeability and inductance.

In this research, we demonstrate the SFCL-based protection theory with an example failure event triggered by a control disturbance. According to Kirchoff’s law, the input voltage vin is equal to the average of the voltages across the SFCL, the inductor, and the on-state MOSFET

$$V_{in}=V_{SFCL}(t)+L\frac{di(fault)}{dt}+V_{MOS}$$

(6)

where the quench behaviour of superconductivity causes the SFCL voltage $V_{SFCL}$ to follow a power-law distribution

$$V_{SFCL}(t)=E_c{S}_{SFCL}{\left(\frac{i(fault(t))}{i(t)}\right)}^v=i_{fault}(t)R_{SFCL}(t)$$

(7)

where $Ec$ is the superconductor’s critical electric field, $1 \mathrm{V}/\mathrm{cm}$; $S_{SFCL}$ is the total tape used to wind the SFCL’s non-inductive coil; and $i_{fault}$ is the SFCL’s transitory over current. The critical current Ic varies nonlinearly with $temperature T$ in real time

$$I_c=I_{co}\left({\left(\frac{1-T}{T_c}\right)}^v\right)$$

(8)

where nI and nT are two material-based indices that indicate the transient quenching process with respect to the operating current and temperature, and Ic0 is a fitted constant equal to the ideal critical current of the superconductor at 0 K. Therefore, the SFCL’s equivalent resistance is denoted by:

$$R_{SFCL}=\frac{E_c{S}_{SFCL}{\left(i_{fault}(t)\right)}^{vT}}{I_{co}\left({\left(\frac{1-T}{T_c}\right)}^v\right)}$$

(9)

When an on-state MOSFET experiences a malfunction, it is protected against thermal runaway if the junction temperature is kept below its maximum threshold Tmax

$$\frac{Q_{MOS}(t)}{A{V}_{volume}\rho c}+T_0\le T_{\max }$$

(10)

where $T_0$, c, and Vvolume represent the initial temperature, heat capacity, material density, and thermal volume, respectively. Using characteristics of thermal diffusion, a suitable parameter of constant A is found. The integral of the instantaneous power during the failure can be used to calculate the heat created inside the on-state MOSFET.

$$Q_{MOS}(t)=\underset{0}{\overset{i_{fault}}{\int }}{V}_{MOS}(t)i_{fault}(t)$$

(11)

3.2. Configuration of Reistive SFCL

There is a series connection between RSC1 and RSC2, and a parallel connection between RSC1 and CLR. This DC SFCL makes use of two superconducting elements to distribute the load more effectively. Superconducting components can save power with the help of a CLR. The RSC1 part cuts the voltage in half, even with a small fault current. In the event of a high fault current, the RSC1 and RSC2 elements work in sequence to sever the current in half. The two levels of triggering current are set once the DC SFCL has been designed.

3.3. Configuration of DC SFCL with Transformer

To facilitate switching between the two current levels and to give the power system more placement possibilities, a DC SFCL with transformer was developed.

To generate alternating current in an SFCL, a superconducting RSC2 element is wired to the secondary side of a transformer and supplied with power in proportion to the turn ratio of the transformer. Changing the transformer’s turn ratio in this DC SFCL affects the current at which quench occurs in RSC2.

If the CLR element can shoulder some of the load normally carried by the superconducting element, then the latter may be able to tolerate less power without sacrificing fault current efficiency. Alternating current (AC) systems can have a variety of different trigger current values, as shown in Figure 5.

The use of a transformer in the construction of a DC SFCL is depicted in Figure 6. In the CLR, the current through RSC2 is proportional to the turn ratio of the transformer (N1/N2), just as it is in the DC SFCL. If the fault current increases the normal-flowing RSC1 current above its critical value, the resistance of RSC1 will increase due to quenching. Since RSC1 is in charge of generating resistance, the DC SFCL can now use a transformer to regulate DC fault current. When current flows into Rsc1, it does so in two directions: along Rsc1 and the CLR, where it meets resistance. The turn ratio of a transformer determines how quickly current flows from the primary (N1) or CLR winding to the secondary (RSC2) winding. When the current in RSC2 exceeds its critical current, the same phenomenon occurs. When utilised to limit DC fault current, this transformer-based SFCL exhibits a quench in the RSC2 area. DC SFCLs can reduce DC fault currents by concurrently quenching RSC1 and RSC2, owing to their dual-triggering current levels.

3.4. Materials and Methods

The proposed DC SFCL has its fault current limiting capabilities tested using a transformer short circuit. As seen in Figure 6, the DC SFCL with transformer is implemented in an experimental circuit.

Three phases of diodes in a bridge rectifier were used to change the alternating current (AC) ES voltage into direct current (DC) (VDC). When SS, the primary power supply switch, is closed, S1 and S2 will turn on.

Current flows exclusively through RLoad when connected in series with S1. S2 is closed and all power is going to RLoad and RFire. Assuming RLoad to be the real load, the DC short-circuit current can be determined by dividing the short-circuit current by this value. After S1 was connected to RLoad and closed at 0.1 s, S2 was set to close for 0.3 to 0.4 s to simulate the increased current from the short circuit. As a safety precaution, the master switch (represented by the letter SS) was flipped off.

The diagram shows a transformer with its primary winding connected in parallel to two superconducting components, RSC1 and RSC2. One of the CLR’s two terminals was wired in series with the primary winding of the transformer and the RSC1 superconducting element. The YBCO thin films were kept in a superconducting condition at 77 K by being stored in cryostats containing liquid nitrogen.

To avoid overheating, each superconducting component was connected to a shunt resistance. A shunt resistance of 2.3 was determined to be the bare minimum necessary when considering the typical superconducting element’s resistance of 80 to 100. Theoretically, the overall resistance will be reduced if the shunt resistor has a lower value than the superconducting component. The integration of a DC SFCL into a DC experimental circuit that makes use of a transformer is depicted in Figure 7.

In the flux–flow zone (where E (t, T) > E0 and T (t) Tc), the superconductor temperature is found to be: (1). When T (t) > Tc, the superconductor should be quenched. Equation (12) can also be written as,

$$T(t)=T_a+\frac{1}{C_{sc}}\underset{0}{\overset{1}{\int }}\left[Q_{sc}(t)-Q_{removed}(t)\right]dt$$

(12)

$$\frac{dT}{dt}=\frac{1}{C_{sc}}\left[Q_{sc}(T)-Q_{removed}(T)\right]$$

(13)

$$\frac{dT}{dt}=\frac{1}{C_{sc}}\left[i(t)E(t,T)I_{SC}-\frac{T(t)-T_a}{{\varphi }_{sc}}\right]$$

(14)

E is the function of temperature

$$\int dt=\int \frac{dt}{\frac{1}{C_{sc}}\left[i(t)E(t,T)I_{sc}-\frac{T(t)-T_a}{{\varphi }_{sc}}\right]}$$

(15)

The duration of the fault is denoted by the time parameter T (t), which is expressed in seconds. The superconducting materials can be thought of as having two properties: temperature, denoted by Q, and conducting power, denoted by C. An inaccuracy E will occur if the incorrect current flow I is used. To measure the rate of heat transfer in a C superconductor, one can utilise the angular momentum change associated with an increase in temperature (denoted by Q in the thermodynamic notation).

Table 2. Materials and parameters.

DC Test Circuit	Value	Unit
VCC	110	Volts
RLOAD	10.5	Ohm
RFIRE	2	Ohm
Transformer CLR	Value	Unit
N1/N2	3	---
CLR(RS)	5.4	Ohm
CLR(LS)	6.6	mH
RSC1 RSC2	Value	Unit
Fabrication Type	Thin Film	---
Material	YBCO	---
Critical Current	20	A

provides a concise overview of the key aspects of the experimental circuit, including the superconducting components. By adjusting the CLR’s resistance and inductance to three different values from Table 2, we can examine the DC fault-current-limiting characteristics of this SFCL.

E (T) is formulated as it is in Equation (16):

$$E(t)=E_0\frac{E_c{}^{\frac{\beta /T}{R}}}{E_0}\frac{1}{C_{sc}}{\left[i(t)E(t,T)I_{sc}-\frac{T(t)-T_a}{{\varphi }_{sc}}\right]}^{\beta }$$

(16)

I and Isc, as well as the non-temperature-dependent portion of E (T), may be merged in the following way [17]:

$$I_{sc}E(T)=I{E}_0\frac{E_c{}^{\frac{\beta /T}{R}}}{E_0}\frac{1}{C_{sc}}{\left[i(t)E(t,T)I_{sc}-\frac{T(t)-T_a}{{\varphi }_{sc}}\right]}^{\beta }{I}_{sc}$$

(17)

$$k=I_{sc}E(T)E_0\frac{E_c{}^{\frac{\beta /T}{R}}}{E_0}{J}_0\frac{J^{\frac{\beta /T}{R}}}{J_0}$$

(18)

$$\int dt=\int \frac{dt}{IE(T)E_0\frac{E_c{}^{\frac{\beta /T}{R}}}{E_0}{J}_0\frac{J^{\frac{\beta /T}{R}}}{J_0}}$$

(19)

$$t=\frac{1}{C_{sc}}arc\tan {\left[i(t)E(t,T)I_{sc}-\frac{T(t)-T_a}{{\varphi }_{sc}}\right]}^{\beta }{I}_{sc}$$

(20)

For each error output E that is delivered, the absolute error of the updated output EO will decrease. Using an exponential model, time is represented by a coefficient.

When the CLR component is a resistance, as shown in Figure 8 and Figure 9, the voltage and current waves look like (a) and (b). In under 0.3 s, SW2 was closed, causing a DC fault current to flow. Voltages were instantly generated in the primary winding and in both superconductors (VSC1 and VSC2) when DC faults occurred (VN1). Figure 8 depicts the voltages of two superconducting components after an immediate overshoot of the critical current (IC) (ISC1, ISC2).

4. Results and Discussion

This model is a MATLAB simulation. Table 1 summarises the most common setting choices. In both the safety system and the R-SFCL, the triggering current is the same (It). The recommended value for the circuit’s capacitor is 10F. We determined that a resistance of 20 Ohms and a critical time constant of 0.5 ms will provide the best practical realisation of SFCL (Tsc). Direct current has a maximum breaking current of 6 kA. Parameters used in simulation are displayed in

Table 3. Parameters used in simulations.

UDC	L	IO	IT	Rf	Rmb
160 kv	25 mH	0.6 kA	1.2 kA	10 Ohm	1 Ohm

.

4.1. Waveforms with and without CLR

Figure 8 and Figure 9 depict the current and voltage waveforms with and without the CLR component acting as a resistance. The DC fault current resulted from SW2 closing in 0.3 s. As can be seen in Figure 8, the primary winding (VN1) and the two superconducting elements (VSC1 and VSC2) experience an immediate increase in voltage after a DC fault. Figure 8 depicts the simultaneous exceeding of the critical current (IC) by currents flowing into two superconducting elements (ISC1, ISC2). This results in voltages in both elements.

Figure 8 shows that 0.31 s after the DC fault, the current in RSC1 (ISC1) quickly dropped while currents in the primary winding and RSC2 (IN1, ISC2) increased. The current in RSC1 (ISC1) increased continuously, but the current in RSC2 (ISC2) and the primary winding (IN1) dropped dramatically 0.31 s after the fault current occurred. The current through the superconducting element RSC2 stopped when the voltage supplied to it was zero, as shown in Figure 8. This happened about 0.33 s after the voltage was removed.

In spite of the fact that current is not flowing via the secondary winding (RSC2), it is flowing through the primary winding (IN1). The high magnetising inductance of the transformer’s iron core explains such fact. DC SFCL with a parallel construction comprising the RSC1 and the transformer incorporating RSC2 has been analysed to increase the limited current in the load. Once the current in RSC1 is reduced by quench, the load current is divisible into those of the superconducting element RSC1 (ISC1) and the primary winding of the transformer (IN1) (IFCL).

The RSC2 (ISC2) current is larger than three times the primary current due to the transformer’s turn ratio (IN1). The current in the primary winding of the transformer (IN1), also known as the CLR, did not considerably increase in the initial fault time even though the currents flowing into both superconducting elements (ISC1 and ISC2) looked to surpass the critical current. A decrease in voltage across the primary winding of the transformer may be seen in Figure 9 as time passes. Current and voltage waveforms for RS = 4.6 are shown in Figure 9 and Figure 10, and they are nearly identical to those for RS = 2.3 except that the amplitude of the induced voltage in the primary winding of the transformer (VN1) is much smaller in the latter case. It was discovered that the voltage in the primary winding of the transformer follows a pattern that is different from the voltage across the CLR (VCLR) (VN1).

The instantaneous power waveforms of RSC1, RSC2, and CLR are depicted in Figure 10. When the voltage of the RSC2 superconducting element (VSC2) recovers to zero following a defect, the initial increased power demand in the RSC1 superconducting element (PSC1) is shared with the CLR, as shown in Figure 10 with RS = 1.15. Figure 10 shows that the power load in RSC1 with an RS = 4.6 CLR was greater than that in RSC2 with an RS = 2.3 CLR, despite the lower resistance of the RS = 1.15 CLR.

Figure 8 demonstrates that there was a sizable power difference between RSC1 and RSC2 when their CLRs began to diverge. Furthermore, a CLR with an RS = 2.3 required somewhat more energy than a CLR with an RS = 4.6, as seen in Figure 8. It was shown that the power load in RSC1 may be raised while the power burden on the CLR was lowered by raising the CLR’s resistance.

Using the CLR’s inductance, the current waveform is depicted in Figure 11. When RSC1 is used as the CLR for the limited DC SFCL current, as shown in Figure 7, the current flows in two directions: into RSC1 and the main of the transformer (IFCL) (ISC1, IN1). In the event of a direct current fault, the current through the RSC2 superconducting element rises gradually, passing the critical current only at the “3” point (the “2” point). Peak current in RSC2 decreases when the CLR’s inductance rises, as seen in Figure 9. In general, a greater CLR inductance slows the rate at which the RSC2 current decays to zero from its greatest value (“4” point). Figure 9 shows that the CLR’s larger inductance did not immediately result in DC fault current limiting as RSC2’s current approached its maximum value. As can be shown in Figure 9, one single CLR can function as an inductance.

Following a DC fault, the VCLR rapidly increases to the peak positive value, lowers to the peak negative value, passes through zero, and then increases again. It is hypothesised that variations in the primary transformer winding (IN1) are linked to the resistance created by the superconducting element (RSC2). As seen in Figure 6, IfCL is distributed predominantly between the primary winding of the transformer (IN1) and the superconducting element RSC1 as the current in RSC2 approaches zero (the “4” point). While RSC1 and RSC2 resistances are decreasing, this is still the case (ISC1). Power waveforms of the RSC1 and RSC2 are shown in Figure 11 due to the inductance of the CLR. As the DC SFCL inductance increases from 6.6 to 10 mH, the RSC2 superconducting element’s peak instantaneous power (PSC2) takes longer to reach its first peak value.

Similar to how the CLR with resistance increases, the power loads on RSC1 (PSC1) and RSC2 (PSC2) are seen to be increased in Figure 6 (higher). The power load in the RSC2 superconducting element (PSC2) disappears almost instantaneously when VSC2 gets to zero, as shown in Figure 11, independent of the value of the CLR inductance.

4.2. IEEE-39 Bus System for Testing

Simulations and data collection for this investigation were carried out in MATLAB. The IEEE 39 bus New England test system was used to verify the accuracy of the suggested technique (depicted in Figure 13). Buses 17, 21, 26, and 28 have all had three-phase short circuits, however, none of these have been replicated in this simulation. Due to the critical nature of transient performance, we restrict our investigation to the lines connected to the aforementioned four buses. The researchers concluded that SFCLs should not be placed at the intersections of lines 18-17, 17-16, 27-17, 21-16, 22-21, 26-25, 29-26, 27-26, 28-26, and 29-28.

Table 4. Line and length of bus system.

Line	Length (kms)
18-17	45.5
17-16	41.5
27-17	51.6
21-16	110.3
22-21	114.9
26-25	203.5
29-26	360.5
27-26	391.83
28-26	209.5
29-28	165.67

displays a compilation of these line lengths. One method of determining a bus’s annual fault rate is dividing it by the sum of the fault rates of the lines that feed into it. Fault rates for four buses are displayed in

Table 5. Fault rate of high risk selected bus.

Bus Number	17	21	26	28
Fault Per Year	0.23	0.14	0.578	0.22
Fault Probability	0.01	0.045	0.078	0.034

along with the occurrence rate of these catastrophic events. Simulation parameters are displayed in

Table 6. Simulation parameters.

Simulation Parameters	Value
Primary Inductance	50 Mh
Secondary Inductance	50 Mh
Mutual Inductance	45 Mh
Ressitance of Supercondcuting Core	5 Ohm

along with parameter values.

Based on SFCL characteristics, the fault current from the microgrid to the PCC is depicted in Figure 12 (taking the A-phase for example). Fast and reliable interruption of fault current is achieved via an electromagnetic switch in SFCL. Since DG units often contribute so heavily to the fault current, its maximum amplitude is usually not very high, although current-limiting effects become more apparent as SFCL design parameters are increased. Figure 12 compares PCC voltage with and without SFCL during an external fault (A-phase). Without SFCL, the PCC voltage is only 53% of what it should be. By increasing PCC voltage, the SFCL helps the IIDG unit better tolerate power outages.

Examining the IEEE 39 bus testing system as shown in Figure 13, the DC current in the superconducting coil is greater than the fault current contributed by DG when the fault is remote from the DG position. Because the limiting impedance of the saturated-core SFCL is so small, it has no effect on the fault current contribution of the DG in this situation and cannot be used to re-establish the recloser-fuse coordination. To solve this issue, reduce the DC current in the superconducting coils, as doing so raises the impedance of the saturated-core SFCL in normal conditions, leading to higher losses and voltage drop. Figure 14 compares the voltage profile (in PU) of the New England grid before and after SFCL installation.

Figure 13. IEEE 39 bus testing system.

Figure 13. IEEE 39 bus testing system.

The

Table 7. Generator Configurations.

Generators	Confugrations	Renewable Energy Units
G2	I	PV
G3	I	PV
G4	I	PV
G7	I	PV
G10	I	PV
G2	II	Wind
G3	II	Wind
G4	II	Wind
G7	II	Wind
G10	II	Wind
G2	III	Battery
G3	III	Battery
G4	III	Battery
G7	III	Battery
G10	III	Battery

summarises our ten available generator setups, each of which makes use of one of three distinct renewable energy units:

IEEE bus 39 rotor speed vs. time is depicted in Figure 15. Where f is the frequency and P is the number of poles, the synchronous speed of the rotor, in revolutions per minute (RPM), is equal to 120 times the frequency of the stator current.

IEEE bus 39 frequency vs. time is depicted in Figure 16. The period of a wave is the time it takes to oscillate or vibrate once, and is defined as being equal to the inverse of the wave’s frequency. The number of vibrations that take place in one second is the definition of frequency, which is the inverse of the time period.

The multimeter can also be used to determine the frequency of an AC voltage signal. A signal’s frequency is the number of times its cycle occurs every second. For example, if a sine wave repeats every 10 s, its frequency is 10 Hertz (Hz). Frequency measured at the source voltage is depicted in Figure 17.

Battery energy storage systems (BESSs) can control reactive power on the grid if their inverters are high-tech enough. Power factor regulation and reactive power support for the grid are two additional functions that can be performed by a battery energy storage system in a microgrid. The BESS VSC active power is displayed in Figure 18 and the BESS VSC reactive power is displayed in Figure 19.

4.3. Test Condition: Single Line to Ground Fault ($L-G$) and Three-Phase Fault

The F1 feeder is subjected to an $L-G$ malfunction between 1.4 and 1.6 s during this test. Because phase A of a three-phase supply is shorted to ground during this failure, the voltage on phases B and C is raised while phase A is at zero (as depicted in Figure 20).

As can be seen in Figure 21 and Figure 22, during a fault condition, the SFCL injects voltage for phase A and then limits that voltage to a constant value that keeps the load voltage constant.

In Figure 17, we can see that during a three-phase fault, all of the phase voltages are at zero. Figure 18 shows the failure interval of 1.4 to 1.5 s during which the SFCL injected the necessary voltage, and Figure 19 shows the resulting constant load voltage.

All the phase voltages are shown to be zero during the three-phase fault in Figure 23. The SFCL injected the required voltage from the failure interval of 1.4 to 1.5 s, as in Figure 24 and maintained a constant voltage in Figure 25.

5. Conclusions

This research focuses on the fault-current-limiting properties of a flux-coupled type superconducting fault current limiter (SFCL) connected in parallel between two windings in a DC system. Two coils need to be connected in parallel, and a superconducting element (SE) is wired in series with the secondary coil to make an SFCL (superconducting flux-coupled coil). Similar to its role in AC systems, the flux-coupled SFCL serves a similar function in DC systems. In the absence of a problem, it was found that the voltage generated by the two parallel coils is zero because the magnetic fluxes generated by each coil are equal. Due to the SE faults, resistance increases, preventing the mutual cancellation of magnetic fluxes and thus causing energy loss. Since the voltage produced by the two coils is small, the fault current is also limited. There is no difference in the triggering current between the safety system and the R-SFCL (It). 10F is the value that is suggested to be used for the capacitor in the circuit. We have come to the conclusion that a resistance of 20 ohms and a critical time constant of 0.5 ms will produce the most optimal realization of SFCL in practical terms (Tsc). The highest current that may be carried by direct current is 6000 A.