A Hybridization of Cuk and Boost Converter Using Single Switch with Higher Voltage Gain Compatibility

Abstract

In the current era, the desire for high boost DC-to-DC converter development has increased. Notably, there has been voltage gain improvement without adding extra power switches, and a large number of passive components have advanced. Magnetically coupled isolated converters are suggested for the higher voltage gain. These converters use large size inductors, and thus the non-isolated traditional boost, Cuk and Sepic converters are modified to increase their gain by adding an extra switch, inductors and capacitors. These converters increase circuit complexity and become bulky. In this paper, we present a hybrid high voltage gain non-isolated single switch converter for photovoltaic applications. The proposed converter connects the standard conventional Cuk and boost converter in parallel for providing continuous current mode operation with the help of a single power switch, which gives less voltage stress on controlled switch and diodes. The proposed hybrid topology uses a single switch with a lower component-count and provides a higher voltage gain than non-isolated traditional converters. The converter circuit mode of operation, operating performance, mathematical derivations and steady-state exploration and circuit parameters design procedures are deliberated in detail. The proposed hybrid converter circuit components, voltage gain and performance, were compared with other topologies in the literature. The MATLAB/Simulink simulation study and microcontroller-based experimental laboratory prototype of 150 W were implemented. The simulation study and experimentation results were confirmed to be a satisfactory agreement with the theoretical analysis. This topology produced non-inverting output in continuous input current mode using a single switch with high voltage gain (≈5.116 gain) with a maximum efficiency of 92.2% under full load.

1. Introduction

Due to the increase in energy demand, large amounts of conventional energy have been consumed, which is very dangerous due to their CO2 emissions. For example, all countries are keen on replacing conventional energy sources with non-conventional sources. Researchers are currently exploring power converters and interfacing circuits to meet out-migration. Non-conventional sources such as wind energy [1,2], photovoltaic (PV) [3,4] and hydrogen-powered fuel cells (FC) [5,6] are leading sources for meeting commercial and industrial demands. A PV-powered power system consists of PV modules coupled in a series as well as parallel combinations that are fed to the required DC voltage through the DC-to-DC converter, which is then converted as a DC-to-AC source through the inverter [7]. The controller development of DC-to-DC converters using a fuzzy logic controller and sliding mode control has recently gained attention. Those converters are used in a microgrid that minimizes the instability effects in [8,9]. For optimizing the performance of the converter, an optimization algorithm was used to tune the controller’s coefficients [9]. A constant power load in a shipboard DC microgrid was investigated for the finite time by adopting the finite-time disturbance observer method [10]. The estimated load power was then received by the fixed-time terminal sliding mode controller to stabilize the entire marine power grid as well as tracking the reference voltage of the DC bus in a fixed time independent of initial conditions. For a high-efficiency PV system, a dual-power stage micro-inverter (high voltage gain DC-to-DC converter + DC-to-AC inverter) was issued in the market. In many industrial applications such as those found in the automotive, telecommunication and shipping industries, systems need higher voltage gain DC-to-DC converters with large input current [11,12,13]. These converters typically boost the range from 24–60 V to 100–300 V. For example, automotive headlamps need 48/100/120 V range, but the vehicle battery capacity can only deliver 12/24/48 V. For these situations, high voltage converters are suggested with high voltage gain [14,15]. According to the theoretical calculations, the conventional boost converter can offer a high duty ratio with infinite voltage gain. However, in a practical case, it is limited due to the inductor saturation limits. Besides, any DC-to-DC converter, which needs to provide a high output voltage and high power conversion, draws large input current; hence, the power switches metal-oxide-semiconductor field-effect transistor (MOSFET) and diode) are needed to handle the voltage stress.

Topologies have presented numerous single switch converters in the literature to provide the high step-up voltage conversion [14,15,16,17,18,19,20]. These converters have some limitations for their voltage gain, which is mainly because of the inductors, power semiconductor switches and the parasitic elements of those converters. Hence, a researcher has recommended using a step-up transformer with a converter to overcome this issue (flyback converter) [21]. It may be achieved with a high current for high power uses, which is not the most efficient. Other attempts have been made by using a single switch with a forward and tapped inductor connected converters are proposed for high voltage gain [22,23,24]. Though these converters have a controlled degree of freedom through the transformer turns ratio adjustment, considering the transformer size, the converter is large. The high voltage gain quadratic converters are the next choice in this group [25,26]. However, a quadratic converter has high voltage stress across the first semiconductor, resulting in it being more efficient than the classical converter. The impedance (using two inductors and two capacitors) source-based converter handles the buck-boost voltage conversion with high gain; however, it needs a high voltage-handling power switch to operate shoot-through and not shoot-through operation. A high voltage gain integrated boost and flyback converter is proposed by [27] using the leakage inductor energy recirculation in the switch-off period; however, this method suffered from pulsating input currents.

The converter topology accumulated with a coupled inductor produces a high step-up conversion with high efficiency [28,29]. Here, the voltage gain is dealt with by changing the converter switch turns ratio like isolated type converters. Though this topology obtains a high gain, due to the coupled inductor-leakage inductance, the switch may suffer a high voltage spike. The passive and active clamping approaches have been established [30] by adding a coupled inductor for the high voltage conversion ratio; however, this converter is inefficient in terms of cost and size. The other choice is adapting a switched capacitor in the switching-mode converter for the high voltage gain [28,29]. Due to the pulse shape, the input current of the converter leads to a weak load and line regulation problems. The voltage-doubler concept in converters [30,31,32,33,34] can provide a high voltage gain with the coupled inductor. Here, the switching frequency is less than an inductor magnetizing current frequency, which is not suitable for reliable operation. Recently, using the single switch in DC-to-DC power converters, various research papers have been published to derive high voltage gain without using a higher duty ratio [35,36,37,38,39,40]. The authors in [33] proposed a 2D/1-D voltage gain single switch buck–boost converter with low input current ripple and appropriate voltage gain. Nevertheless, it has the discontinuous current in the input side. In paper [37], a transformerless high voltage gain buck–boost was proposed with a voltage gain of 3D/1-D; though this converter has a discontinuous input current. A quadratic DC–DC buck–boost converter with single-switch topology is presented in [39] for widespread voltage conversion. The high step-up single switch converter is recommended for PV-based grid applications [30]. However, in this converter, the low-level input voltage habitually roots massive input current and higher current ripples. This large amount of current affects the power switch during the higher duty ratio operation, causing a large conduction loss. Recently, Banaei et al. proposed a converter using a single switch with less switching voltage stress. Even though the converter can maintain the continuous input current for all duty ratios, the primary power switch voltage stress is strictly equal to the converter output voltage, which caused high conduction losses [38]. In [40,41], the single switch Cuk topology uses an extra inductor and capacitor to provide the extra voltage. However, in this topology, when diodes are operating with higher current and voltage, the diode reverse recovery current is predominant, which increases the switching losses. Among all converter topology, the cascade boost converter type is proficient in obtaining a higher gain with minimal duty ratio for the full range of voltage gain [19]. Nevertheless, the main switch has higher voltage stress in this topology.

Based on this discussion, and although several single switch boost converter topologies are proposed in the literature, their major approaches are concerned with the use of less magnetic elements, size, weight, conduction losses and cost-savings for the inductors. These approaches have higher voltage stresses on their switch (nearly the same as their output voltage). Therefore, these converters still have significant challenges, such as high step-up requirements for the larger duty ratio, output diode reverse recovery complication, higher switching voltage stress and satisfactory efficiency. Integrating the classical DC-to-DC converter is a better choice than modifying an existing converter. However, while cascading those classical converters with additional boosting capability, reducing the power switches and passive elements leads to an appropriate converter circuit size as well as cost reductions. With that aim, in this paper, we propose a DC–DC converter topology by integrating the conventional boost and Cuk converters with high voltage gain. Our proposed topology uses only one power switch with higher static voltage gain when compared to other conventional converters. Our proposed converter delivers voltage using two series-connected identical capacitors connected in parallel with the converter circuit. In this paper, we also deal with the maintenance of the capacitor balancing. The detailed converter mode operation, analysis, design, small-signal analysis and analytical switching losses were deliberated. The MATLAB/Simulink simulation and PIC microcontroller-based experimentation results for the integrated converter shows the advantages and practicality of the proposed converter.

The paper is organized as follows: Section 2 describes the proposed hybrid converter design and its mode of operation. Section 3 describes the converter components design and small-signal analysis. Section 4 explains the design procedure and components. The simulation, experimentation and comparison with other similar topologies are discussed in Section 5 and Section 6. The conclusion is given at the end of Section 7.

2. Topology and Operation of Proposed Hybrid DC–DC Converter

The proposed integrated hybrid converter combines the conventional boost converter and classical Cuk DC-to-DC converter. The method used for the design of the proposed hybrid converter topology is illustrated in Figure 1. Figure 1a,b shows the typical conventional boost converter and classical Cuk converter, respectively. In both of these converters, the input inductor, power switches and input source are organized in the same way. Hence, there is an opportunity to merge these two converters by keeping the power switch and input inductor commonly on the input side. Except for the input side boost inductor (L₁) and the power switch T, the rest of the circuit is connected precisely in parallel with each other. Hence, the output side two capacitors (C₁ and C₃) are placed across the load. This hybrid structure increases the voltage gain by complementing the benefits of boost and Cuk converters. The converter provides continuous current mode operation with the help of a single power switch, which provides less voltage stress on the controlled switch and diodes.

Operation of Hybrid DC–DC Converter

The proposed hybrid DC–DC converter mode operations, their capacitors (C₁, C₂ and C₃) and inductors (L₁ and L₂) charging and discharging analysis derivations were considered as follows. The two assumptions were taken for this analysis: (1) all the components are ideal; (2) the converter works under continuous conduction. Figure 3a illustrates the continuous conduction operating mode waveforms of the proposed converter. This advanced hybrid DC–DC converter mode operation has three modes of operation.

• Mode-I [t_a–t_b], presented in Figure 2a. During mode-1, when t = t_a, the power switch T is turned ON and inductors (L₁ and L₂) are charging until t_b. In the same interval, the capacitor C₂ is discharging through T, and inductor L₂ as the diodes (D₁ and D₂) are blocking concerning V_C1 and V_C2.
• Mode-II [t_b–t_c], illustrated in Figure 2b. During mode-1, when t = t_b, the power switch T is in the OFF state. Now the capacitor C₁ voltage (V_C1) is higher than V_C2. Hence, after t_b interval, the C₂ is charging and inductors L₁ and L₂ are discharging. It is happening throughout t_b to t_c. In the course of this period, diode D₂ is continuously conducting since diode D₁ is still in reverse bias.
• Mode-III [t_c–t_d], presented in Figure 2c. During this mode, the power switch T remains OFF as well as the V_C1 is equal or lesser than V_C2. Here, both the inductors L₁ and L₂ are discharging, and C₁ and C₂ are charging via L₁. Hence the diode D₁ and D₂ are conducting and delivering the current to load.

The proposed hybrid DC-to-DC converter operation mode waveforms are presented in Figure 3. In mode-I, the power switch T is ‘ON’ and turned ‘OFF’ in mode-II as well as mode-III. The proposed converter duty ratio versus voltage gain performance was compared to boost and Cuk converters. Figure 3b displays the voltage gain versus duty ratios for boost, Cuk and the proposed hybrid converter. Based on the plot, it can be seen that the proposed hybrid converter has a better voltage gain ratio when compared with the boost and Cuk converter, respectively. In addition to the extended voltage static gain, the proposed topology achieves lower voltage stress across the power switch and diodes, when compared to a boost converter.

The power switch voltage stress is equal to the peak voltage across the capacitor C1. Hence, voltage stress across the power switch T was lower than the total output voltage. The voltage stress of D1 and D2 is equal to the voltage across the power switch T in the OFF state. Hence, the diodes’ current rating requirement was lower than power switch T. In the classical boost converters for both Cuk and boost, the power switch and diode need an equal rating. In the higher gain operations, the classical converter needs a higher duty cycle than the proposed converter. Therefore, the voltage stress for switch and diode are higher. Hence, the proposed converter efficiency in the higher gain operation is better than the conventional boost converter.

Figure 2. Modes of operation of the proposed hybrid DC-to-DC converter: (a) Mode-I [t_a–t_b]; (b) Mode-II [t_b–t_c]; (c) Mode-III [t_c–t_d].

Figure 2. Modes of operation of the proposed hybrid DC-to-DC converter: (a) Mode-I [t_a–t_b]; (b) Mode-II [t_b–t_c]; (c) Mode-III [t_c–t_d].

Figure 3. (a) Mode diagram of the proposed circuit; (b) voltage gain versus duty ratio for boost, Cuk and proposed hybrid converter.

Figure 3. (a) Mode diagram of the proposed circuit; (b) voltage gain versus duty ratio for boost, Cuk and proposed hybrid converter.

In general, for any DC-to-DC converter, the input inductor selection is carried out depending on the converter conduction mode, load current requirement, and it is desirable to confirm the least output current ripple. Hence, the input inductor L₁ value was chosen with minimal current ripple ∆_iL. The inductor current, i_L for the proposed converter is supplied from either a PV or DC source (V_PV or V_in). When the converter receives a supply voltage from the input source, the converter power switch T is turned ON, and inductor current i_L1 is derived as follows. Applying Kirchhoff’s voltage law in mode-I [t_a–t_b], the capacitors current i_C1 and i_C2 are derived as

$$\begin{gathered} -V_{PV}+v_{L1}=0\Rightarrow v_{L1}=V_{PV} \\ -v_{C2}+v_{L2}+v_{C3}=0\Rightarrow v_{L2}=-v_{C3}+v_{C2} \end{gathered}$$

(1)

$$\begin{gathered} -i_T+i_{L1}-i_{C2}=0 \\ {i}_O-i_{L2}-i_{C3}=0 \end{gathered}$$

(2)

$$\begin{gathered} i_{C2}=-i_{L2} \\ {i}_{C1}=-i_O \end{gathered}$$

(3)

During mode-II [t_b–t_c], when the power switch T is in OFF, the coil transfers energy to the capacitors C₁ and C₃. As a result, from loop 1 and loop 2, it can verify that

$$\begin{gathered} -V_{PV}+v_{L1}+v_{C2}=0\Rightarrow v_{L1}=-v_{C2}+V_{PV} \\ {v}_{L2}+v_{C3}=0\Rightarrow v_{L2}=-v_{C3} \\ {v}_{C2}=v_{C1} \end{gathered}$$

(4)

From loop 1 and loop 2 (mode-II Figure 2b), the capacitor current i_C1 and i_C2 are derived as follows,

$$\begin{gathered} i_{C1}=i_{D1}-i_O \\ {i}_{C2}=i_{L1}-i_{D1}=i_{D2}-i_{L2} \end{gathered}$$

(5)

$$I_C=\frac{1}{T}\underset{0}{\overset{T}{{\displaystyle \int }}}{i}_{C}dt=\frac{C}{T}\underset{0}{\overset{T}{{\displaystyle \int }}}d{v}_C\left(t\right)=\frac{C}{T}\left(v_C\left(T\right)-v_C\left(0\right)\right)$$

(6)

during steady-state condition V_C(T) = V_C(0). Hence, the average value of the current capacitors is null. Also, the inductor coils average voltage is zero, since $v_L\left(t\right)=L\frac{d{i}_L\left(t\right)}{dt}$. The currents in the inductors and voltage in the capacitors tend to be approximately constant. The power switch is in the ON state for a percentage of the period (δT) and OFF during the next state (δT-T). Here, T is the total switching time. Therefore, the average value inductor voltage V_L1 and capacitor’s current i_C1 are illustrated in Figure 4 and Figure 7.

$$V_{L1}=\frac{1}{T}\left[\underset{O}{\overset{\delta T}{{\displaystyle \int }}}{V}_{PV}dt+\underset{\delta T}{\overset{T}{{\displaystyle \int }}}\left(V_{PV}-V_{C1}\right)dt\right]=0_{}$$

(7)

Replacing the voltage on the calculation, we obtain the capacitor voltage V_C1

$$V_{C1}=\frac{1}{1-\delta }{V}_{PV}$$

(8)

The inductor L₂ voltage is illustrated in Figure 5, and inductor average voltage value is

$$V_{L2}=\frac{1}{T}\left[\underset{0}{\overset{\delta T}{{\displaystyle \int }}}\left(V_{C1}-V_{C3}\right)dt+\underset{\delta T}{\overset{T}{{\displaystyle \int }}}-V_{C3}dt\right]=0$$

(9)

The voltage across the capacitor C₃ can be written as

$$V_{C3}=\frac{\delta }{1-\delta }{V}_{PV}$$

(10)

Hence, the converter output voltage can be calculated as

$$V_O=\frac{1+\delta }{1-\delta }{V}_{PV}$$

(11)

By equating the converter input power and output power, the input inductor current is derived as

$$V_{PV}{I}_{L1}=V_O{I}_O\Rightarrow I_{L1}=\frac{1+\delta }{1-\delta }{I}_O$$

(12)

When the Kirchhoff’s current law is applied in the loop

$$i_{C3}+i_O-i_{L2}=0\Rightarrow i_{L2}=i_{C3}+i_O$$

(13)

The capacitor C₃ charge and discharge current is shown in Figure 6. Here the capacitor current average value observed is zero, and the average current in the inductor is similar to the average output current, as the inductor tends to retain that average value.

Assuming that i₀ = i_l2

The mean value of the capacitor C₁ current (i_C1) is displayed in Figure 7. From the capacitor current interval zero to δT and δ to T time, the i_C1 is calculated as

$$I_{C1}=\frac{1}{T}\left[\underset{0}{\overset{\delta T}{{\displaystyle \int }}}\left(-i_O\right)dt+\underset{\delta T}{\overset{T}{{\displaystyle \int }}}\left(i_{D1}-i_O\right)dt\right]=0$$

(14)

$$i_{D1}-i_O=i_O\frac{\delta }{1-\delta }$$

(15)

When the power switch T is turned ON, the diode D₁ current is calculated as

$$i_{D1}=\frac{I_O}{1-\delta }$$

(16)

Similarly, when the power switch T is turned OFF, the diode D₂ current is calculated as

$$i_{L1}-i_{D1}=i_{D2}-i_{L2}=I_O\frac{\delta }{1-\delta }$$

(17)

$$i_{D2}=\frac{I_O}{1-\delta }$$

(18)

The current of the power switch T can be written as

$$i_T=i_{L1}-i_{C2}=\frac{2I_O}{1-\delta }$$

(19)

3. Scaling Converter Components Design

The proposed hybrid converter reactive components, inductors coil (L₁ and L₂) and capacitors (C_1, C₂ and C₃), are calculated for maximum values as the power switch T should support both the converter voltage and current.

3.1. Design of Inductors

The inductor coil (L₁ and L₂) values calculation and current limitation analysis are observed by precise variation concerning the average value shown in Figure 8. The differential equation of inductor voltage V_L is shown as

$$v_L\left(t\right)=L\frac{d{i}_L\left(t\right)}{dt}$$

(20)

By assuming inductor voltage V_L nearly constant, the current equation inductor is calculated as follows

$$i_L\left(t\right)=\frac{v_L}{L}\Delta t_L+i_L(t0)$$

(21)

Thus, $v_L\left(t\right)=L\frac{d{i}_L\left(t\right)}{dt}$ it becomes

$$\frac{\Delta i_L}{\Delta t_L}=\frac{v_L}{L}$$

(22)

Using the instantaneous inductor voltage equation, the inductor voltage will be

$$v_{L1}=\{\begin{array}{l}{V}_{PV},nT<t<nT+\delta T\\ V_{PV}-V_{C1},nT+\delta T<t<\left(n+1\right)T\end{array}$$

(23)

During ‘ON’ state of the power switch, $\Delta t_L$ = $\delta T$

$$L_1=\frac{V_{PV}\delta T}{\Delta i_{L1}}$$

(24)

$$v_{L2}=\{\begin{array}{l}{V}_{C1}-V_{C3,}nT<t<nT+\delta T\\ -V_{C3,}nT+\delta T<t<\left(n+1\right)T\end{array}$$

(25)

For the ‘OFF’ state of the power switch, it has $\Delta t_L=\left(1-\delta \right)T$

$$L_2=\frac{v_{\mathrm{C}3}\left(1-\delta \right)T}{\Delta i_{L2}}$$

(26)

3.2. Design of Capacitors

The calculation of capacitor values C₁, C₂ and C₃ are given below. The changing and discharging variation around the average value is shown in Figure 9.

The differential equation of the capacitor

$$i_c\left(t\right)=C\frac{d{v}_c\left(t\right)}{dt}$$

(27)

Similar to the calculation of inductors, the capacitor variation is calculated using Equation (27) after linearization of $i_c\left(t\right)=C\frac{d{v}_c\left(t\right)}{dt}$ becomes,

$$\frac{\Delta v_c}{\Delta t_c}=\frac{i_C}{C}$$

(28)

With the instantaneous value of the capacitor current over a certain period, the value of the capacitor can be calculated. For capacitor C₁, the current is given by:

$$i_{C1}=\{\begin{array}{l}-I_0,nT<t⥂<nT+\delta T\\ I_0\frac{\delta }{1-\delta },nT+\delta T<t<\left(n+1\right)T\end{array}$$

(29)

During the first-time interval, for ∆t_c = δT, C₁ is

$$C_1=\frac{I_0\delta T}{\Delta v_{C1}}$$

(30)

The capacitor current C₂ is given by

$$i_{C2}=\{\begin{array}{l}-I_0,nT<t⥂<nT+\delta T\\ I_0\frac{\delta }{1-\delta },nT+\delta T<t<\left(n+1\right)T\end{array}$$

(31)

During the time interval, when ∆t_c = δT

$$C_2=\frac{I_0\delta T}{\Delta v_{C2}}$$

(32)

For capacitor C₃, the current does not show instantaneous values and is nearly constant during the switching state. The behavior of capacitor C₃ is opposite capacitors C₁ and C₂. When controlling the power semiconductor switch for the driving load variation, capacitor charge ∆Q is related to the inductor current ∆i_L2/2 and time is taken T/2.

$$Q=C{v}_c\Rightarrow C=\frac{Q}{v_c},C_3=\frac{\Delta Q}{\Delta v_{c3}}$$

(33)

$$\mathrm{At}\mathrm{load}\mathrm{variation},\Delta Q=\frac{\frac{T}{2}\frac{\Delta i_2}{2}}{2}=\frac{T\Delta i_{L2}}{8}$$

(34)

$$\mathrm{The}\mathrm{capacitor}{C}_3\mathrm{value}\mathrm{is}\mathrm{calculated}\mathrm{as}{C}_3=\frac{T\Delta i_{L2}}{8\Delta v_{c3}}$$

(35)

In the dynamic condition, capacitors C₁ and C₃ values are deliberate in this section. The calculation is computed by including the sudden change in drive load resistance. Output voltage in the dynamic operating region is determined using the equivalent circuit (Figure 10 and Figure 11), assuming that the current passes zero to its steady-state value, ∆t₁, the settling time of the current in the inductor L₁.

$$i_{C1}=C_1\frac{d{v}_{C1}}{dt}=-i_0\Rightarrow v_{C1}\left(t\right)=\frac{1}{C_1}\underset{0}{\overset{t}{{\displaystyle \int }}}\left(-i_0\right)dt+v_{C1}\left(0\right)$$

(36)

$$v_{C1}\left(\Delta t_1\right)=\frac{1}{C_1}\underset{0}{\overset{t}{{\displaystyle \int }}}\left(-i_0\right)dt+v_{C1}\left(0\right)=-\frac{1}{C_1}\frac{P_0}{V_0}\Delta t_1+v_{C1}\left(0\right)$$

(37)

Thus, capacitor voltage VC₁ is calculated using Equation (37)

$$v_{C1}\left(\Delta t_1\right)=\frac{1}{C_1}\underset{0}{\overset{t}{{\displaystyle \int }}}\left(-i_0\right)dt+v_{C1}\left(0\right)=\frac{1}{C_1}\frac{P_0}{V_0}\Delta t_1\Rightarrow C_1=\frac{1}{\Delta v_{C1}}\frac{P_0}{V_0}$$

(38)

In a dynamic case, while changing the converter duty ratio, the inductor current increases coil rapidly. Hence, the ∆t₁ value needs to calculate, in detail, from the response of i_LI(s), which displays the input current of the response when rapid changes occur in output current i_o(s). At time ∆_t2, the current flow through the capacitor C₃ is calculated as

$$i_{C3}=C_2\frac{d{v}_{C3}}{dt}=-i_0$$

(39)

$$C_3=\frac{1}{\Delta v_{C3}}\frac{P_0}{V_0}\Delta t_2$$

(40)

For calculation straightforwardness, it is assumed that the current has equal settling times.

In terms of the energetic properties, the proposal converter is similar to the boost and Cuk converters. The proposed converter input inductor, power switches and input source are organized the same way as the classical boost and Cuk converters. Except for the input side boost inductor (L₁) and the power switch T, the rest of the proposed converter circuit elements are connected precisely in parallel with each other and on the output side, two capacitors (C₁ and C₃) are placed across the load. Therefore, the proposed converter increases the voltage gain by combining the benefits of boost and Cuk converters.

3.3. Small Signal Analysis of Hybrid DC–DC Converter

The average equivalent circuit model of the proposed hybrid DC–DC converter was derived and is presented in Figure 10. The circuit analysis was derived for the switch in both the ON and OFF period. The initial conditions were an approach to obtain the average value of the coil; the current remained the same.

By the application of mesh law to the circuit in Figure 10, we can verify that

$$\{\begin{array}{l}-V_{PV}+v_{L1}+r_{L1}{I}_{L1}+R_{DSon}⥂i_T=0\\ v_{C2}-v_{L2}-R_{DSon}{i}_T-vc3-r_{L2}{I}_{L2}=0\end{array}\Rightarrow \{\begin{array}{l}{v}_{L1}=-V_{PV}-r_{L1}{I}_{L1}-R_{DSon}⥂i_T\\ v_{L2}=v_{C2}-R_{DSon}{i}_T-v_{C3}⥂-r_{L2}{I}_{L2}\end{array}$$

(41)

$$\{\begin{array}{l}-V_{PV}+v_{L1}+r_{L1}{I}_{L1}+v_{C2}+V_{D2}+R_{D2}⥂i_{D2}=0\\ v_{L2}+r_{L2}{I}_{L2}+v_{C3}+V_{D2}+R_{D2}{i}_{D2}=0\end{array}\Rightarrow \{\begin{array}{l}{v}_{L1}=-V_{PV}-r_{L1}{I}_{L1}-v_{C2}-V_{D2}-R_{DSon}⥂i_T\\ v_{L2}=-r_{L2}{I}_{L2}-v_{C3}-V_{D2}-R_{D2}{i}_{D2}\end{array}$$

(42)

$$-V_{PV}+v_{L1}+r_{L1}{I}_{L1}+v_{C1}+v_{D1}+R_{D1}{i}_{D1}=0$$

(43)

$$v_{D1}=v_{D2},R_{D1}{i}_{D1}=R_{D2}{i}_{D2},v_{C2}=v_{C1}$$

From the waveform $v_{L1}$ and $v_{L2}$,

$$V_{L1A}=V_{PV}-R_{Dson}{I}_T-r_{L1}{I}_{L1}$$

(44)

$$V_{L1B}=V_{PV}-r_{L1}{I}_{L1}-V_{C1}-V_{D2}-R_{D2}{I}_{D2}$$

(45)

$$V_{L2A}=V_{C1}-R_{DSON}{I}_{SC}-V_{C3}-r_{L2}{I}_{L2}$$

(46)

$$V_{L2B}=-r_{L2}{I}_{L2}-V_{C3}-V_{D2}-R_{D2}{I}_{D2}$$

(47)

The analysis of converter input to output relation is calculated with losses and approximated with ideal semiconductor devices. The output voltage expressions of the converter were derived and are given below.

$$V_{L1}=0\Rightarrow V_{C1}=\frac{V_{PV}-r_{L1}{I}_{L1}}{1-\delta }$$

(48)

$$V_{L2}=0\Rightarrow V_{C3}=\frac{\delta }{1-\delta }\left(V_{PV}-r_{L1}{I}_{L1}\right)-r_{L2}{I}_{L2}$$

(49)

From the expressions V_C1 and V_C2, the voltage gain converter is calculated as

$$\frac{V_0}{V_{PV}}=\frac{1+\delta }{1-\delta +\frac{r_{L1}}{R_0}\frac{{\left(1+\delta \right)}^2}{1-\delta }+\frac{r_{L2}}{R_0}\left(1-\delta \right)}$$

(50)

where r_L1/R₀ = r_L2/R₀.

Figure 12 illustrates the voltage output gain versus the duty cycle for the proposed hybrid converter. The Figure indicates the ideal condition (r_L1/R₀ = 0), where losses need to be introduced in the circuit (the gain for unit value goes to zero, as expected) and other operating conditions r_L1/R₀ = r_L2/R₀ = 0.0001 to 0.76, where near 0.76 duty cycle, the converter gain approaches six times boosting (V₀ = 6V_in).

3.4. Analysis of Losses

The losses of each indictor L₁ and L₂ are denoted from internal resistors r_L1 and r_L2, respectively. Thus, the losses in r_L1

$$P_{⥂r_{L1}}=p_1⥂P_i⥂=r_{L1}{I}_{L1rm{s}^2}\iff r_{L1}=\frac{p_1{P}_i}{I_{L1rms}{}^2}$$

(51)

The sufficient value is given as

$$I_{L1rms}=\sqrt{I_{L1}{}^2+{\left(\frac{\Delta i_{L1}}{2\sqrt{3}}\right)}^2}=\sqrt{I_{L1}{}^2+{\left(\frac{0.1I_{L1}}{2\sqrt{3}}\right)}^2}=I_{L1}\sqrt{1+{\left(\frac{0.1}{2\sqrt{3}}\right)}^2}$$

$$\Delta i_{L2}=0.1I_{L2}$$

(52)

$$\mathrm{Sin}\mathrm{ce}\mathrm{both}\mathrm{the}\mathrm{inductors}\mathrm{are}\mathrm{identical},\Delta i_{L1}=0.1I_{L1}$$

(53)

Two kinds of losses in the semiconductor are driving and switching.

3.5. Conduction Losses in the Diodes

The losses in the diode are given as

$$P_D=\frac{1}{T}\underset{0}{\overset{T}{{\displaystyle \int }}}{v}_D\left(t\right)i_D\left(t\right)dt=V_D{I}_D+R_D{I}_{Drms}^2$$

(54)

$$v_D\left(t\right)=V_D+R_D{i}_D\left(t\right)$$

(55)

Specific to the case of the diode, for mode-2 operation:

$$i_{D1}\left(\delta T<t<T\right)=\frac{I_0}{\left(1-\delta \right)}$$

(56)

$$I_{D1}=\frac{1}{T}\underset{0}{\overset{T}{{\displaystyle \int }}}{i}_{ak1}\left(t\right)dt=I_0$$

(57)

$$I_{D1rms}=\sqrt{\frac{1}{T}\underset{0}{\overset{T}{{\displaystyle \int }}}{i}_{D1}^2\left(t\right)dt}=\frac{I_0}{\sqrt{\left(1-\delta \right)}}$$

(58)

Thus, resistance is calculated as

$$P_{D1}=\frac{p_3}{2}{P}_i=V_{D1}{I}_0+R_{D1}{\left(\frac{I_0}{\sqrt{\left(1-\delta \right)}}\right)}^2\iff R_{D1}=\left(\frac{p_3}{2}{P}_i-V_{D1}{I}_0\right)\frac{\left(1-\delta \right)}{I_0^2}$$

(59)

The same can be applied to D_2, resulting in the same results for this diode

$$R_{D2}=(\frac{p_3}{2}{P}_i-V_{D2}{I}_0)\frac{\left(1-\delta \right)}{I_0^2}$$

(60)

4. Design Procedure

The component selections and other design parameters of the proposed converter at the power range of 150 W were calculated and are presented. The input power was considered a DC-fixed source. The general diagram of the converter design flow chart is shown in Figure 13.

To illustrate the numerical values of converters, capacitor and inductors, the below parameters were fixed for the converter design.

• The input power P_in = 150 W, for V_in = 24 V, I_in = 6.2 A;
• Power of the converter, P_i = 150 W;
• Input voltage converter V_in = 24 V;
• Duty cycle is fixed as δ = 0.8;
• The converter output voltage, V_o = 104 V;
• The output current and inductor current were expected to be I₀ = 1.11 A and I_L1 = 4.25 A, respectively;
• The capacitor C₁ and C₃ voltages were calculated as V_C1 = 110 V and V_C3 = 104 V;
• The general typical value sizing of capacitor C₁, C₃ and L₁, L₂ was calculated as ∆i_L1 = 10% I_L1, hence for L₁ = 1 mH, the change in this was ∆i_L1 = 0.425 A. The same changes can be seen for ∆i_L2 = 10% I_L2, L₂ = 1 mH and ∆i_L2 = 0.14 A;
• When the change in the capacitor ∆V_C1 was 1% V_C1, the capacitor C₁ value was 100 μF and ∆V_C1 = 1.10 V. Similarly, for ∆V_C2 = 1% V_C2, C₂ = 100 μF, ∆V_C2 = 1.04V and ∆V_C3 = 1% V_C3, C₃ = 2 μF,∆V_C3 = 0.08 V;
• For the power semiconductor switch, the maximum open-circuit voltage was Vs_max = 100 V, Vs_max = 95 V;
• Diodes D₁ and D₂, Vs_max = 100 V, Vs_max = 95 V.

The D₁ and D₂ can ensure a voltage of 100V, which ensures the safety factor of the converter. The converter can support a maximum current of six amps. When using six amps, the current safety factor is reduced to 60%–65%. Hence, the semiconductor must be selected to withstand the converter to provide maximum currents and voltages with a safety factor around 50%. The n-type reinforcing MOSFET is better chosen for providing the safety factor, and the proposed converter design uses the same [35]. The diodes (D₁ and D₂), and MOSFET switching losses and conduction losses were calculated and given in Equations (61)–(73).

Conduction losses of the diode D₁ and D₂:

$${\mathrm{P}}_{\mathrm{D}}={{\displaystyle \int }}^{\text{}}{\mathrm{V}}_{\mathrm{ak}}\left(\mathrm{t}\right){\mathrm{i}}_{\mathrm{ak}}\left(\mathrm{t}\right)dt={\mathrm{V}}_{\mathrm{D}}{\mathrm{i}}_{\mathrm{ak}+}{\mathrm{R}}_{\mathrm{D}}{I}_{akrms}^2$$

(61)

$${\mathrm{R}}_{\mathrm{D}1}=\left(\frac{p3}{2}{\mathrm{p}}_{\mathrm{i}}-{\mathrm{V}}_{\mathrm{D}1}{\mathrm{I}}_{\mathrm{o}}\right)\frac{\left(1-\delta \right)}{I_o^2}$$

(62)

$${\mathrm{R}}_{\mathrm{D}1}=\left(\frac{p3}{2}{\mathrm{p}}_{\mathrm{i}}-{\mathrm{V}}_{\mathrm{D}2}{\mathrm{I}}_{\mathrm{o}}\right)\frac{\left(1-\delta \right)}{I_o^2}$$

(63)

$${\mathrm{P}}_{\mathrm{D}1}={\mathrm{V}}_{\mathrm{D}1}{\mathrm{i}}_{\mathrm{ak}1+}{\mathrm{R}}_{\mathrm{D}1}{I}_{akrms1}^2$$

(64)

$${\mathrm{P}}_{\mathrm{D}2}={\mathrm{V}}_{\mathrm{D}2}{\mathrm{i}}_{\mathrm{ak}2+}{\mathrm{R}}_{\mathrm{D}2}{I}_{akrms2}^2$$

(65)

Switching losses of the Diode D₁ and D₂:

$${\mathrm{P}}_{\mathrm{SD}1}=\frac{{\mathrm{t}}_{\mathrm{rr}}-{\mathrm{t}}_{\mathrm{s}}}{\mathrm{T}}{\mathrm{V}}_{\mathrm{ak}1}{\mathrm{i}}_{\mathrm{ak}1}$$

(66)

$${\mathrm{P}}_{\mathrm{SD}2}=\frac{{\mathrm{t}}_{\mathrm{rr}}-{\mathrm{t}}_{\mathrm{s}}}{\mathrm{T}}{\mathrm{V}}_{\mathrm{ak}2}{\mathrm{i}}_{\mathrm{ak}2}$$

(67)

Conduction losses of the MOSFET:

$${\mathrm{P}}_{\mathrm{MOSFET}\mathrm{Conduction}\mathrm{Loss}}={\mathrm{R}}_{\mathrm{DS}\_\mathrm{ON}}{\mathrm{i}}_{\mathrm{MOSFET}\mathrm{rms}}$$

(68)

$${\mathrm{i}}_{\mathrm{MOSFET}}=\frac{2I_0}{\left(1-\delta \right)}$$

(69)

$${\mathrm{P}}_{{\mathrm{P}}_{\mathrm{MOSFET}\mathrm{switcing}\mathrm{loss}}}=\frac{{\mathrm{t}}_{\mathrm{ON}}+{\mathrm{t}}_{\mathrm{OFF}}}{\mathrm{T}}({\mathrm{V}}_{\mathrm{MOS}}{\mathrm{i}}_{\mathrm{MOS}})+\frac{1}{2\mathrm{T}}{\left({\mathrm{C}}_{\mathrm{MOS}}{\mathrm{V}}_{\mathrm{MOS}}\right)}^2$$

(70)

Total switching losses for the proposed converter is:

$${\mathrm{P}}_{\mathrm{total}\mathrm{switcing}\mathrm{losses}}=\frac{{\mathrm{t}}_{\mathrm{ON}}+{\mathrm{t}}_{\mathrm{OFF}}}{\mathrm{T}}({\mathrm{V}}_{\mathrm{MOS}}{\mathrm{i}}_{\mathrm{MOS}})+\frac{1}{2\mathrm{T}}{\left({\mathrm{C}}_{\mathrm{MOS}}{\mathrm{V}}_{\mathrm{MOS}}\right)}^2+2\frac{{\mathrm{t}}_{\mathrm{rr}-}{\mathrm{t}}_{\mathrm{s}}}{\mathrm{T}}{\mathrm{V}}_{\mathrm{ak}}{\mathrm{i}}_{\mathrm{ak}}$$

(71)

$${\mathrm{t}}_{\mathrm{ON}}={\mathrm{t}}_{\mathrm{r}}\left({\mathrm{i}}_{\mathrm{MOS}}\right)+{\mathrm{t}}_{\mathrm{f}}({\mathrm{V}}_{\mathrm{MOS}})$$

(72)

$${\mathrm{t}}_{\mathrm{OFF}}={\mathrm{t}}_{\mathrm{f}}\left({\mathrm{i}}_{\mathrm{MOS}}\right)+{\mathrm{t}}_{\mathrm{r}}({\mathrm{V}}_{\mathrm{MOS}})$$

(73)

The efficiency of the proposed converter is found using

$$\eta =\left(\frac{{\mathrm{p}}_{\mathrm{o}}}{{\mathrm{p}}_{\mathrm{i}}}\right)=\frac{{\mathrm{P}}_{\mathrm{i}}-{{\displaystyle \sum }}^{\text{}}{\mathrm{P}}_{\mathrm{T}}}{{\mathrm{P}}_{\mathrm{i}}}$$

(74)

where P_i = input power and ∑P_T= Total losses (P _{Diode2 Con.Losses} + P_{Diode2 Con.Losses} + P_{MOSFET switching loss} + P_{MOSFET Conduction Loss}).

5. Simulation Results

The hybrid DC–DC converter operation and performance estimation were modeled in the MATLAB/Simulink simulation platform and waveforms were presented. The simulation specification and parameter were as follows: The input power = 150 W, input voltage of the converter (V_in) = 24 V, maximum duty cycle δ = 0.8 and switching frequency f_s = 10 kHz. The converter input and output inductors were L₁ = 1 mH and L₂ = 1 mH receptivity. The capacitors were C₁ = 100 μF, C₂ = 100 μF and C₃ = 2 μF. Figure 14, Figure 15, Figure 16 and Figure 17 show the proposed converter simulation results for 10 kHz switching frequency and 80% duty cycle, and the results confirm the theoretical values. The converter duty cycle was fixed to be equal to or less than 0.8 to minimize the conduction losses. From Figure 14, when the converter duty cycle was fixed at 0.8 with 24V input voltage, the converter delivered an output voltage of 124 V (5.166 times higher than the input voltage). During the continuous conduction mode, the inductance L1 current was limited within the saturation limit in the range of 3 to 4.5 A and maintained the converter input current. Figure 15 displays the input current, as well as voltage across the power switches, and Figure 17 shows D₁ and D₂ voltages, V_D1 and V_D2, respectively, during the switching period. From the results, it could be seen that during the time of switching, the switches (MOSFET and diode) were maintained with their maximum allowable voltage as 100 V. It was verified that the voltage across the switches was less than that of the converter. From the i_L2 and V_D2 simulation results, it can be seen that the proposed converter maintains a continuous current capability. Figure 16 shows the simulation waveforms for the inductor current i_L1 and inductor current i_L2. From this waveform, it is seen that the inductors were charging uniformly and delivering the current in the continuous conduction. Figure 17 illustrates the voltage across the power diode, V_D1 and V_D2. When the duty cycle was reduced to 0.6, the converter performance, switching reliability and continuous current capability were linear. Hence, the proposed converter has a wide range of controllability with a controlled degree of freedom to avail wider voltage outputs. The simulation was also performed in transient conditions (changing load and sudden change in the duty cycle). During this transient period, the output voltage and current through i_L1 changed with a small transient period and after reaching the continuous conduction and maintaining the constant output voltage.

The proposed single switch hybrid DC–DC converter is compared with conventional converters (boost and Cuk) for different duty cycles from the range zero to one. The switching frequency and other circuit components for this evaluation were taken as being the same as the proposed converter values are given in the design (see

Table 1. Parameter of components of the proposed converter.

Components	Parameter
Input power Pinput	150 W
Input voltage Vin	24 V
Output power P0	112 W
Switching frequency fs	10 KHz
Power MOSFET	SiHB30N60E
Diode D1 and D2	VS-15EWX06FN-M3
Inductance L1 and L2	1 mH
Capacitor C1,C2 and C3	100 μF, 100 μF and 2 μF
The output of Diode VD1 and VD2	100 V and 95 V
Output Capacitor VC1,VC2 and VC3	104 V, 110 V and 8 V

). As expected, the proposed converter voltage gain was more than the boost and Cuk converter duty cycle. Figure 18 shows the voltage gain comparison of boost and Cuk with the proposed converter.

6. Experimental Results

To confirm the experimental performance of the proposed hybrid DC–DC converter, the experimental laboratory setup was developed in collaboration with a Peripheral Interface Controller (PIC) microcontroller, as shown in Figure 19. To verify the theoretical and simulation results, the experimentations were conducted with similar values considered in the simulation studies. The converter was a 150 W circuit with parameters as listed in Table 1.

Similar to the simulation verification, the converter duty cycle was fixed as equal to or less than 0.8 to minimize the conduction losses. While testing the converter, the input DC source was fixed to generate constant input voltage and power as 24 V and 150 W range. As seen in Figure 20, while the converter duty cycle was fixed as 0.8, the corresponding output voltage was observed to be 122 V (closer to the simulation results). Figure 21 shows the converter input current and output voltage.

During the DC-to-DC conversion period, the converter maintained the continuous conduction with the inductance L₁ current saturation limit range of 3 to 4.5 A, as depicted in Figure 22. Hence, the power switch was secured against the high rising current by maintaining the converter input current inductance L₁ current saturation limit, which ensures the converter reliability against the input source. Similarly, from Figure 23 and Figure 24, during the time of switching, the MOSFET and diode were maintained with their maximum allowable voltage as 100 V, which was smaller than the converter output voltage (102 V). Here, during the switching period, the voltage across the main power switch was 100 V, and diode D₁ and D₂ were equal to V_D1 = 100 V and V_D2 = 95 V, respectively. During the entire mode of operation, the inductor current i_L1 and i_L2 maintained the identical current profile, which maintains the voltage balance between C₁ and C₂. Figure 25 shows the experimental waveform of the input inductor current, i_L1 and voltage across i_D2 the power switch for input voltage 24 V and 0.8 duty cycle.

Next, the converter was operated by changing the duty ratio to observe transient operation behaviour. For the period of transient operation, the converter load was kept constant as the previous value. During the trial, the switching duty-cycle varied from 0.8 to 0.5. During this period, likely the output voltage decreased and stabilized after a few milliseconds. A similar response happened in the inductor current i_L1 and preserved in the converter in continuous conduction.

To validate the comparison of the theoretical and experimental results, the converter continuous conduction mode(CCM) state voltage gain was plotted concerning the variation duty ratio from 0.2 to 0.8 (see Figure 26a). From the results, it can be seen that the experimental values are very close to the theoretical calculations. Finally, the efficiency of the proposed converter was found under full load. The calculated experimental maximum efficiency of the proposed converter at 0.8 duty cycle is 92.2%. The calculated experimental maximum efficiency of the proposed converter is 92.2%. Figure 26b shows experimental power loss distribution operating at the rated condition. During duty ratio δ = 0.8, the semiconductors (D₁, D₂ and MOSFET) switching losses were calculated as 0.4 W, 0.5 W and 1.2 W using equations (61)–(74). Hence, the total switching losses for the converter was 2.1 W. Similarly, the conduction of the power switches and other circuit parameters losses were observed. In the overall power distribution losses, the MOSFET switching loss and conduction loss alone are about 52%. As presented in Figure 26b, the I²R losses in the MOSFET, diode and the snubber circuitry losses were accounted for as significant losses. Nevertheless, the proposed converter voltage stress reduction helps to choose the lower voltage-rating switch, and hence conduction losses are expected to reduce.

Key Performance Comparison

For validating the proposed converter performance,

Table 2. Performance comparison of similar converter topology.

Similar Converter Topology	Converter [39]	Converter [9]	Converter [30]	Converter [40]	Converter [36]	Proposed Converter
Switches used	1	2	1	1	1	1
Diodes used	5	2	2	3	1	2
No. of Inductors used	3	2	2	3	2	2
No. of capacitors used	3	2	3	3	3	3
Continuous input current	Yes	No	Yes	Yes	No	Yes
Voltage gain, VO	$\frac{{\left(\delta \right)}^2}{{\left(1-\delta \right)}^2}\mathrm{Vin}$	$\frac{2\left(1+\delta \right)}{\left(1-\delta \right)}\mathrm{Vin}$	$\frac{1}{1-\delta }\mathrm{Vin}$	$\frac{\delta }{{\left(1-\delta \right)}^2}\mathrm{Vin}$	$\frac{2\delta }{\left(1-\delta \right)}\mathrm{Vin}$	$V_O=\frac{1+\delta }{1-\delta }{V}_{PV}$
Efficiency	91%	90%	91%	90%	92%	92.2%
The voltage stress on the active switch	Moderate	Less	High	Less	High	Moderate

shows the comparison with other similar converters. According to the table, the proposed converter provides a better voltage gain with a single active switch, and normalized voltages stress of semiconductor devices is less when compared to other converters. Based on the presented analysis and discussions, results and comparisons confirm the functionality and advantages of the proposed converter.

7. Conclusions

The high voltage gains and highly efficient single switch hybrid non-isolated DC–DC converter is shown in this paper. The proposed topology was derived by integrating conventional boost and Cuk converters. This topology produced a non-inverting output in continuous input current mode with a single switch having high voltage gain (≈5.116 gain). When compared with the classical boost and Cuk converters, the proposed topology facilitates a substantial voltage gain with comparable lower switching stress. The steady-state analysis under the CCM condition and design calculation for the proposed hybrid was discussed in detail.

Finally, the validation test done with the proposed converter privileges, the voltage gain, power switch voltage stress and elements used in the circuit simulation studies were presented. Characterize the proposed topology for its obtained performances, PIC microcontroller based real-time experimental setup was realized under the power rating of 150 W with an efficiency of 92.2%. Experimental results confirmed the practicability in real-time applications needs.