Multi-Port Multi-Directional Converter with Multi-Mode Operation and Leakage Energy Recycling for Green Energy Processing

Abstract

In this article, a novel multi-port multi-directional converter (MPMDC) is proposed. Even though the power stage of the MPMDC belongs to a single-stage structure, it can control power flow direction handily among ports and achieve converter operation in up to five modes. The MPMDC has the feature of galvanic isolation and can obtain a high voltage conversion ratio even under the adoption of only one inductor and one transformer. The leakage energy of the transform can be recycled to improve overall efficiency. Once the MPMDC is applied to deal with renewable energy, battery, and bus energy, the advantage of multi-directional control of power flow can advance an energy storage system to perfectly function power conditioning feature. In addition to the discussion of converter operation, voltage gain, voltage stress, current stress, and inductance design are analyzed theoretically. Comparisons with some of the latest similar converters are also carried out. A 200-W prototype is built and measured. According to the practical results, it is verified that the hardware measurements meet the theoretical derivations and the MPMDC is validated. The maximum efficiency of the converter is up to 94%.

1. Introduction

Recently, with the purpose of retarding global warming and climate change, the generation and application of renewable power have been developing rapidly, and especially focusing on solar power [1,2,3,4] and wind turbines [5,6]. However, the usage of these kinds of expeditiously growing energy is highly confined by some problems, such as weather, intermittence, and unstableness. To overcome the problems, incorporating an energy storage system (ESS) to function as the feature of energy conditioning is an effective solution [7,8,9]. The ESS can save the generation power exceeding during periods of light loading and afterwards release its stored energy during periods of heavy loading. The reliability of a power system can accordingly be increased and the imbalance between renewable power supply and load demand can also be alleviated. In addition, owing to the significant growth and expansion of the electrical automobile industry [10,11], the capability and performance of lithium cells have been improving more and more, which enriches the EES market and its related applications as well. It is highly expectable that hybrid-generation systems that combine green energy, a storage system, and utility will be in demand and developed. In this article, a novel power converter is therefore proposed to deal with multiple types of energy sources.

Figure 1a is a conventional PV power system, in which a battery is incorporated to serve as energy backup. Since the PV panels and the battery are both low-voltage sources, for DC-bus connection the system requires two converters to process power individually. One is the unidirectional high-step-up converter (UHSC), which boosts PV voltage to a much higher level [12,13,14], and the other is the bidirectional converter (BC), which performs battery charging and discharging [15,16,17]. However, the traditional structure has disadvantages, such as low total conversion efficiency, high cost, and huge size. To combine the two individual converters into a single one, a multi-port converter (MPC) was developed and has become the current trend. As illustrated in Figure 1b, an MPC, in general, integrates two DC–DC converters into a single-stage structure. In [18,19], the power stages of the MPCs in a single-stage structure are mainly the combination of basic converters. Having a simple structure is their merit, but no isolation and low voltage gain are drawbacks. In [20], the MPC can gain a high conversion ratio, however, in which an input port is in a floating connection. The three ports can be in common connection to yield an easier design of a control circuit [21,22,23]. Nevertheless, these converters still exist with the disadvantage of no galvanic isolation. In [24], the converter is derived by fundamental boost and buck structures to obtain an MPC, in which the power stage is simple but galvanic isolation still cannot be achieved. The converter in [25] incorporates a single core to fulfill the feature of multi-port and to accomplish a variety of operation modes, but it cannot possess the isolation feature and is unable to deal with two different kinds of input energy, limiting its application field toward renewable generation system. The converter utilizes two magnetic devices to carry out multi-port energy processing and can accomplish many operation modes [26]. However, its voltage gain is lower than most structures of MPCs. The MPC can be realized with a lower account of power devices to lower cost [27], nevertheless, in which the input port will influence the function of battery charging. Besides, the input port is floating. The MPCs in [28,29,30,31,32,33] adopt transformers and/or coupled inductors to diminish the problems of non-isolation and low conversion gain. However, it is unavoidable that the converters still have different kinds of shortcomings. The voltage gain of the converter in [28] is low; besides, more magnetic components and active switches have to be required. Even though high voltage gain can be completed in [29,30], the DC bus is incapable of charging the battery. In [31], the converter lacks the function of battery charging from the DC bus and exists the demerit of low voltage gain. Concerning [32], more active power switches must be employed and voltage gain is not as high as expected, both of which are shortcomings.

In order to thoroughly solve all the aforementioned disadvantages, this article proposes a novel multi-port multi-direction converter (MPMDC), as shown in Figure 1c, which has the merits of high voltage-conversion ratio, the feature of galvanic isolation, leakage energy recycling, battery charging/discharging, and multi-direction energy controlling. The MPMDC is aiming at power processing for a microgrid system, not only for a UPS. A microgrid system that incorporates PV panels and battery and then connects to DC bus needs isolation between the PV and battery/bus, but not necessarily between battery and bus. Therefore, the proposed converter is designed without isolation between the battery and the DC bus. The MPMDC can accomplish a variety of system operation modes as many as up to five modes. The power flow direction of each mode is indicated in Figure 2 and described as follows.

• Single input and single output for PV power processing (SISO-PV mode): Only the PV panels forward power to the DC bus, as shown in Figure 2a. In this mode, the battery has been fully charged and PV panels inject all the generated solar power into the DC bus;
• Single input and single output for battery-energy providing (SISO-battery mode): As referred to in Figure 2b, only the battery discharges toward the DC bus. This mode works at night or during a rainy day;
• Dual-input single-output mode (DISO mode): During the heavy-load period, the DC bus must draw sufficient power from the generation system. To meet the load demand, the PV panels and battery will provide energy simultaneously, which is illustrated in Figure 2c;
• Single-input dual-output mode (SIDO mode): The power flow is illustrated in Figure 2d. While in the period of intensive insolation, The PV panels can supply enough power to charge the battery and feed the DC bus as well;
• Back-feeding mode (BF mode): As shown in Figure 2e, under the operation of BF mode, the MPMDC can draw energy from the DC bus to charge the battery.

2. Converter Structure and Operation Analysis

The power stage of the proposed MPMDC is depicted in Figure 3. What the components in Figure 3 stand for are described as follows: the V_pv, V_bat, and V_bus are the voltages of PV panels, battery, and DC bus, respectively; the S₁–S₅ are power switches, which inherently have body diodes D_S1–D_S5 in turn and parasitic capacitances C_S1–C_S5 as well; the D₁–D₅ denote as diodes; the C₁ and C₀ are capacitors, while L₁ expresses inductor; in addition, N₁ and N₂ represent the turns of the primary and secondary windings of the transformer, respectively, and L_m and L_k indicate the magnetizing inductance and leakage inductance of the transformer, respectively.

2.1. Operation Principle

The voltage polarity and current direction of the MPMDC are defined in Figure 4. For the analysis of the converter in steady state, some conditions are made as follows:

• Capacitors C₁ and C₀ are large enough so that the voltage ripples on C₁ and C₀ can be neglected;
• The diodes D₁–D₅ are considered ideal;
• Parasitic capacitance in power switches is very small so that it can be reasonably omitted;
• The leakage inductance L_k is much smaller than the magnetizing inductance L_m;
• The duty ratios of switches S₁ and S₂ are all less than 0.5;
• The turns ratio of the transformer T_r is defined as n and equal to $\frac{N_2}{N_1}$.

2.1.1. SISO-PV Mode

In SISO-PV mode, switches S₁ and S₂ are controlled, that is, both of which are in charge of the role of main switches. While operating in this mode, both switches are turned on and off simultaneously and driven by an identical control signal. The converter operation can be mainly divided into two stages over one switching cycle. The key waveforms of the converter in SISO-PV are depicted in Figure 5. In addition, the corresponding equivalent stages are shown in Figure 6.

Stage 1 [t₀–t₁]

This stage starts at time t = t₀, as shown in Figure 6a. The switches S₁ and S₂ are turned on at the same time, and the diodes D₁–D₅ are all in OFF-state. Over the whole time interval t₀–t₁, that is, the ON-time period D_sw1T, the L_m and L_k both draw energy from PV panels and capacitor C₁. Meanwhile, the output capacitor C_o pumps its stored energy to the DC bus. Since switch S₃ and diode D₃ break the current path of the transformer, therefore, there is no current flowing through the transformer. This stage ends at the time switches S₁ and S₂ are turned off.

Stage 2 [t₁–t₂]

At t = t₁, as shown in Figure 6b, the switches S₁ and S₂ are turned off and diodes D₁–D₄ become in ON-state. The energy stored in L_m has therefore released to the DC bus via the transformer T_r. The PV panels and the magnetizing inductor L_m charge capacitor C₁ simultaneously. The energy of leakage inductance L_k is recycled to capacitor C₁. As switches S₁ and S₂ are turned on again, the operation of SISO-PV mode over period T completes.

2.1.2. SISO-Battery Mode

In SISO-battery mode, the main switches become S₄ and S₅, that is, both of which are turned on and off periodically and complementarily, while the other switches are kept in OFF-state. During this mode, the steady-state operation of the MPMDC can be mainly divided into two stages over one switching cycle. Figure 7 depicts the key waveforms of the converter and Figure 8 is the equivalent stage for each stage.

Stage 1 [t₀–t₁]

As shown in Figure 8a, this stage starts at the time t = t₀. In this stage, switch S₄ keeps closed, and thus the voltage across inductor L₁ will be V_bat. The current flowing through L₁ increases linearly. The capacitor C_o discharges its energy to the load R_o. When switch S₄ is turned off, this stage ends.

Stage 2 [t₁–t₂]

The time interval of this stage is from t₁ to t₂. The equivalent stage is shown in Figure 8b. During this time interval, switch S₅ is in ON-state, whereas S₄ is kept open. The energy stored in L₁ is released to the load R_o, and therefore its current decreases linearly. When S₅ is turned off and the switch S₄ is turned on again, this stage ends.

2.1.3. DISO Mode

In DISO mode, switches S₁, S₂ and S₄ serve as main switches, in which S₁ and S₂ are turned on and off simultaneously; meanwhile, the switch S₄ is also turned on at the same time as S₁ and S₂ but its ON-state will last for a longer time than S₁ and S₂. The operation of DISO can be mainly divided into four stages over one switching cycle. The key waveforms of DISO are depicted in Figure 9. In addition, the corresponding equivalent stage of each stage is illustrated in Figure 10.

Stage 1 [t₀–t₁]

This stage starts at the time t = t₀, of which the equivalent stage circuit is presented in Figure 10a. During the time interval t₀–t₁, switches S₁, S₂ and S₄ are closed and then the magnetizing inductance L_m and leakage inductance L_k absorb energy from the PV panels and capacitor C₁. The battery V_bat is across the inductor L₁ directly and the current flowing through L₁ increases linearly. The capacitor C_o discharges to the load R_o. When the switches S₁ and S₂ are turned off, this stage ends.

Stage 2 [t₁–t₂]

This stage lasts from t₁ to t₂ and Figure 10b is the equivalent stage circuit. Switch S₄ is still in ON-state and diodes D₁ and D₂ are forward biased. The PV panels along with magnetizing inductance L_m release energy to capacitor C₁. At the same time, leakage inductance L_k recycles its energy to capacitor C₁. The battery voltage V_bat is still charging the inductor L₁, and capacitor C_o supplies energy to the load R_o. Since switch S₃ and diode D₃ have broken the current path of the transformer, no current flows through the transformer. This operating stage ends when switch S₄ is turned off.

Stage 3 [t₂–t₃]

At the time t₂, the converter operation enters Stage 3. Figure 10c is the equivalent stage of this stage, in which diodes D₁, D₂, and D₄ are forward biased, and parasitic diodes D_S3 and D_S5 are also in ON-state. The inductor L₁ releases energy to the load R_o through D₄, D_S3, and D_S5. When parasitic diode D_S5 is reversely biased, this stage ends.

Stage 4 [t₃–t₄]

The time interval of this stage is from t₃ to t₄. As shown in Figure 10d, diodes D₁, D₂, D₄, and parasitic diodes D_S3 still keep conducting. The energy stored in L_m and L₁ is simultaneously released to the load R_o. This operation stage ends when switches S₁, S₂, and S₄ have been turned on again.

2.1.4. SIDO Mode

While in SIDO mode, the switches S₁, S₂, and S₃ act as the main switch. The S₁ and S₂ are turned on and off at the same time, that is, both of which are controlled by an identical switching signal. Concerning S₃, it is turned on synchronously as S₁ and S₂ but asynchronously at turn-off time. The converter operation in SIDO can be divided into four stages over one switching cycle. The key waveforms are shown in Figure 11, while the equivalent stages are illustrated in Figure 12.

Stage 1 [t₀–t₁]

This stage starts at t = t₀. Figure 12a is the equivalent stage circuit, in which switches S₁, S₂, and S₃ are turned on at the same time. The series voltage of V_pv and V_C1 is connected to L_m and L_k, and thus the currents i_Lm and i_Lk increase linearly. The secondary of the transformer forwards energy to the inductor L₁ and the load R_o. When the switch S₃ is turned off and the body diode of switch S₄, D_S4, is forward biased, this stage ends.

Stage 2 [t₁–t₂]

The time interval of this stage is from t₁ to t₂, as shown in Figure 12b, in which S₃ is OFF while S₁ and S₂ are still ON. The PV panels and capacitor C₁ keep charging the L_m and L_k. The inductor L₁ releases its stored energy to charge the battery, and capacitor C_o supplies the load R_o. In this state, the current path of the transformer will be broken by switch S₃ and diode D₃. This stage ends when both switches S₁ and S₂ are turned off.

Stage 3 [t₂–t₃]

At t = t₂, Stage 3 begins, whose equivalent stage is shown in Figure 12c. At the primary of the transformer, the diodes D₁ and D₂ become forward-biased, and the energy stored in the L_m and L_k is released to capacitor C₁. There is the same circuit behavior at the secondary of the transformer, in which the inductor L₁ is still charging the battery, and capacitor C_o supplies the load R_o. When the current of inductor L₁ decreases to zero, this stage ends.

Stage 4 [t₃–t₄]

The time in this stage is from t₃ to t₄, as shown in Figure 12d. During this time interval, diodes D₁ and D₂ are still conducted. The magnetizing inductor L_m is continuously charging capacitor C₁, and capacitor C_o supplies the load R_o. This operating stage ends when switches S₁, S₂, and S₃ have been turned on again.

2.1.5. BF Mode

In BF mode, the main switches are S₄ and S₅, which are controlled complementarily. The BF-mode operation has two main stages over one switching cycle. The key waveforms of BF mode are depicted in Figure 13; meanwhile, its corresponding equivalent stages are illustrated in Figure 14.

Stage 1 [t₀–t₁]

As shown in Figure 14a, this stage lasts from t₀ to t₁, in which switch S₅ is ON-state. The voltage of C_o is applied to L₁ and therefore the current flowing through L₁ will increase linearly. This linearly increasing current stops raising at the time switch S₅ is turned off.

Stage 2 [t₁–t₂]

At the moment S₅ is turned off and S₅ is turned on, this stage starts. Stage 2 continues from t₁ to t₂, the equivalent stage of which is shown in Figure 14b. During this stage, the energy of inductor L₁ is released and then charges the battery. This operating stage ends when switch S₅ is turned on again.

3. Steady-State Analysis

To simplify the steady-state analysis of the proposed converter, the following assumptions are made:

• All components are considered ideal;
• All the values of capacitors are large enough to keep their voltage constant during one switching cycle;
• The turns ratio of the transformer T_r is expressed as $n=\frac{N_2}{N_1}$;
• The L_m of the Tr and the inductor L₁ both are operated in CCM.

3.1. Voltage Gain

The voltage-gain derivation toward the operation modes, that is, SISO-PV mode, SISO-battery mode, DISO mode, SIDO mode, and BF mode, are discussed one by one as follows.

3.1.1. Derivation for SISO-PV Mode

As referred to in Figure 6a, the switches S₁ and S₂ are ON, and the series voltage of V_C1 and V_pv is connected to L_m. That is,

$$V_{\mathit{Lm},\mathit{SISO}-\mathit{PV}}=V_{\mathit{pv}}+V_{C1}$$

(1)

When the switches S₁ and S₂ are OFF, as shown in Figure 6b, the difference voltage of V_pv and V_C1 is applied to L_m. In addition, the secondary of the transformer is connected to the load through the diodes D₃ and D₄. Accordingly, the following relationships hold:

$$V_{\mathit{Lm},\mathit{SISO}-\mathit{PV}}=V_{\mathit{pv}}-V_{C1}$$

(2)

and

$${\mathit{nV}}_{\mathit{Lm},\mathit{SISO}-\mathit{PV}}=-V_{\mathit{bus}}$$

(3)

Based on the volt-second balance criterion (VSBC), the voltage gain of bus voltage to PV voltage in SISO-PV mode, M_SISO-PV, is therefore concluded as:

$$M_{\mathit{SISO}-\mathit{PV}}=\frac{V_{\mathit{bus}}}{V_{\mathit{pv}}}=\frac{{2\mathit{nD}}_{\mathit{sw}1}}{{1-2D}_{\mathit{sw}1}},$$

(4)

in which the D_sw1 stands for the duty ratio of S₁. To further understand how the D_sw1 affects the voltage gain M_SISO-PV, the curve to illustrate their relationship is depicted in Figure 15, in which the turns ratio, n, is set to be 1.5.

3.1.2. Derivation for SISO-Battery Mode

In Figure 8a, switch S₄ is closed, and the battery is directly connected to inductor L₁. Then,

$$V_{L1,\mathit{SISO}-\mathit{Battery}}=-V_{\mathit{bat}}.$$

(5)

While switch S₄ is open, the corresponding equivalent stage is shown in Figure 8b, in which the inductor L₁ pumps its stored energy to the bus. That is,

$$V_{L1,\mathit{SISO}-\mathit{Battery}}=V_{\mathit{bus}}.$$

(6)

Similarly, based on VSBC, the voltage gain of the converter in SISO-battery mode can be expressed as:

$$M_{\mathit{SISO}-\mathit{battery}}=\frac{V_{\mathit{bus}}}{V_{\mathit{bat}}}=\frac{D_{\mathit{sw}4}}{{1-D}_{\mathit{sw}4}}.$$

(7)

In (7), the M_SISO-battery denotes the ratio of bus voltage to battery voltage. The relationship between the voltage gain M_SISO-Battery and duty cycle D_sw4 is represented in Figure 16.

3.1.3. Derivation for DISO Mode

To derive the voltage gain of the converter in DISO mode, Figure 10 is referred to. In Figure 10a, switches S₁, S₂, and S₄ are closed. On the primary side of the transformer, magnetizing inductance L_m absorbs energy from the PV panels and capacitor C₁. On the secondary side, the battery charges the inductor L₁. Therefore,

$$V_{\mathit{Lm},\mathit{DISO}}=V_{\mathit{pv}}+V_{C1}.$$

(8)

$$V_{L1,\mathit{DISO}}=-V_{\mathit{bat}}.$$

(9)

When switches S₁ and S₂ are turned off, as shown in Figure 10b, capacitor C₁ will be charged by the PV panels and the L_m. Therefore,

$$V_{\mathit{Lm},\mathit{DISO}}=V_{\mathit{pv}}-V_{C1}.$$

(10)

When switch S₄ is turned off, referred to in Figure 10d, the energy stored in both inductors L₁ and L_m will be released to the load. The voltage across L₁ can be expressed as follows:

$$V_{L1,\mathit{DISO}}=V_{\mathit{bus}}+{\mathit{nV}}_{\mathit{Lm},\mathit{DISO}}=V_{\mathit{bus}}+n\left(V_{\mathit{pv}}-V_{C1}\right).$$

(11)

Then, based on VSBC, the voltage gain of the converter while operating in DISO mode, M_DISO, is therefore found as:

$$M_{\mathit{DISO}}=\frac{V_{\mathit{bus}}}{V_{\mathit{pv}}+V_{\mathit{bat}}}=\frac{{2\mathit{nV}}_{\mathit{pv}}{D}_{\mathit{sw}1}\left(1-D_{\mathit{sw}4}\right)+V_{\mathit{bat}}{D}_{\mathit{sw}4}\left(1-{2D}_{\mathit{sw}1}\right)}{\left(V_{\mathit{pv}}+V_{\mathit{bat}}\right)\left(1-{2D}_{\mathit{sw}1}\right)\left(1-D_{\mathit{sw}4}\right)}.$$

(12)

In (12), it can be observed that both duty cycles of S₁ and S₄ dominate the voltage gain in DISO mode. Figure 17 indicates the relationship between M_DISO, D_sw1, and D_sw4.

3.1.4. Derivation for SIDO Mode

For the derivation of the voltage gain in SIDO, Figure 12a is referred to, in which the switches S₁, S₂ and S₃ are ON. The magnetizing inductor L_m stores energy from the PV panels V_PV and the capacitor C₁. The PV panels and the capacitor C₁ also supply power to inductor L₁ and the load R_o through the transformer. Therefore, the following relationships hold:

$$V_{\mathit{Lm},\mathit{SIDO}}=V_{\mathit{pv}}+V_{C1}.$$

(13)

$$V_{L1,\mathit{SIDO}}={\mathit{nV}}_{\mathit{Lm},\mathit{SIDO}}=n(V_{\mathit{pv}}+V_{C1})=V_{\mathit{bus}}.$$

(14)

When switches S₁ and S₂ are turned off, as shown in Figure 10c, the energy of the magnetizing inductor L_m is released to capacitor C₁. Inductor L₁ will charge the battery V_bat. Accordingly,

$$V_{\mathit{Lm},\mathit{SIDO}}=V_{\mathit{pv}}-V_{C1}.$$

(15)

$$V_{L1,\mathit{SIDO}}={-V}_{\mathit{bat}}.$$

(16)

With VSBC, the voltage gain is concluded as:

$$M_{\mathit{SIDO}}=\frac{V_{\mathit{bat}}}{V_{\mathit{pv}}}=\frac{{2\mathit{nD}}_{\mathit{sw}3}\left(1-D_{\mathit{sw}1}\right)}{\left(1-{2D}_{\mathit{sw}1}\right)\left(1-D_{\mathit{sw}3}\right)}.$$

(17)

Figure 18 indicates the voltage gain M_SIDO versus duty cycles D_sw1 and D_sw3.

3.1.5. Derivation for BF Mode

In BF mode, since the energy is reversely drawn from the DC bus to charge the battery, the voltage gain becomes the ratio of V_bat to V_bus. Referring to Figure 14a, it can be found that because the switch S₅ is closed, the voltage across the inductor L₁ is equal to the bus voltage. That is,

$$V_{L1,\mathit{BF}}=V_{\mathit{bus}}.$$

(18)

After switch S₅ is turned off, as shown in Figure 14b, the energy stored in inductor L₁ is released to charge the battery. That is,

$$V_{L1,\mathit{BF}}=-V_{\mathit{bat}}.$$

(19)

The circuit behavior of the BF mode resembles that of a buck converter. Applying VSBC to the durations of switch-ON and switch-OFF can yield

$$M_{\mathit{BF}}=\frac{V_{\mathit{bat}}}{V_{\mathit{bus}}}=\frac{D_{\mathit{sw}5}}{1-D_{\mathit{sw}5}},$$

(20)

in which the M_BF and D_sw5 indicate the voltage gain of BF mode and duty cycle of switch S₅. Figure 19 depicts this voltage gain versus its related switch cycle.

To clarify the voltage gain of the converter in different modes,

Table 1. Voltage gains of the proposed converter in different modes.

Mode	Voltage Gain
SISO-PV mode	$M_{\mathit{SISO}-\mathit{PV}}=\frac{V_{\mathit{bus}}}{V_{\mathit{pv}}}=\frac{{2\mathit{nD}}_{\mathit{sw}1}}{1-{2D}_{\mathit{sw}1}}$
SISO-battery mode	$M_{\mathit{SISO}-\mathit{Battery}}=\frac{V_{\mathit{bus}}}{V_{\mathit{bat}}}=\frac{D_{\mathit{sw}4}}{1-D_{\mathit{sw}4}}$
DISO mode	$M_{\mathit{DISO}}=\frac{V_{\mathit{bus}}}{V_{\mathit{pv}}+V_{\mathit{bat}}}=\frac{{2\mathit{nV}}_{\mathit{pv}}{D}_{\mathit{sw}1}\left(1-D_{\mathit{sw}4}\right)+V_{\mathit{bat}}{D}_{\mathit{sw}4}\left(1-{2D}_{\mathit{sw}1}\right)}{\left(V_{\mathit{pv}}+V_{\mathit{bat}}\right)\left(1-{2D}_{\mathit{sw}1}\right)\left(1-D_{\mathit{sw}4}\right)}$
SIDO mode	$M_{\mathit{SIDO}}=\frac{V_{\mathit{bat}}}{V_{\mathit{pv}}}=\frac{{2\mathit{nD}}_{\mathit{sw}3}\left(1-D_{\mathit{sw}1}\right)}{\left(1-{2D}_{\mathit{sw}1}\right)\left(1-D_{\mathit{sw}3}\right)}$
BF mode	$M_{\mathit{BF}}=\frac{V_{\mathit{bat}}}{V_{\mathit{bus}}}=\frac{D_{\mathit{sw}5}}{1-D_{\mathit{sw}5}}$

summarizes the expression of M_SISO-PV, M_SISO-battery, M_DISO, M_SIDO, and M_BF.

3.2. Voltage Stresses on the Semiconductors

All semiconductor devices will sustain different levels of voltage and current in different operation modes. The maximum sustained voltage and current among the five modes should be treated as the power rating of a selected semiconductor device. In the following, the estimation of the maximum voltage stress for all semiconductor devices is first carried out, followed by the determination of the maximum current stress in the next subsection.

The S₁, S₂, D₁, and D₂ in the power stage will block the same voltage in the modes of SISO-PV, DISO, and SIDO. This blocking voltage is higher than that in the other modes of the converter. Therefore, to calculate the voltage rating of S₁, S₂, D₁, and D₂, one of the SISO-PV, DISO, and SIDO modes will be considered. According to Figure 6, the blocking voltage is equal to the voltage across C₁. Therefore,

$$V_{S1,\mathit{stress}}=V_{S2,\mathit{stress}}=V_{D1,\mathit{stress}}=V_{D2,\mathit{stress}}=V_{C1}=\frac{V_{\mathit{pv}}}{1-{2D}_{\mathit{sw}1}}.$$

(21)

The switch S₃ will block a maximum voltage in DISO mode and SIDO mode as well. From the equivalent stage in Figure 12b, this blocking voltage is calculated and given below:

$$V_{S3,\mathit{stress}}=n\left(V_{\mathit{pv}}+V_{C1}\right)+V_{\mathit{bat}}={\mathit{nV}}_{\mathit{pv}}\left(1+\frac{1}{1-{2D}_{\mathit{sw}1}}\right)+V_{\mathit{bat}}.$$

(22)

Considering S₄ and S₅, both switches have the highest voltage stress in DISO mode. The voltage stresses of S₅ and S₄ can be determined in Figure 10a,c, respectively. Both voltage stresses are the same and can be given as

$$V_{S4,\mathit{stress}}=V_{S5,\mathit{stress}}=V_{\mathit{bus}}+V_{\mathit{bat}}.$$

(23)

To determine the voltage stress of diode D₃, SIDO mode is considered and the equivalent stage in Figure 12c is utilized, from which it can be concluded that

$$V_{D3,\mathit{stress}}=n(V_{\mathit{pv}}+V_{C1})=n(V_{\mathit{pv}}+\frac{V_{\mathit{pv}}}{{1-2D}_{\mathit{sw}1}}).$$

(24)

The rest of the voltage-stress determination of the semiconductor component is for diodes D₄ and D₅. Diodes D₄ and D₅ endure the same maximum voltage in DISO mode. From Figure 10a, the voltage stresses of both diodes can be found as

$$V_{D4,\mathit{stress}}=V_{D5,\mathit{stress}}=V_{\mathit{bus}}.$$

(25)

3.3. Current Stresses on the Semiconductors

The semiconductor devices, S₁, S₂, D₁, and D₂, identically undergo maximum current stress in SISO-PV mode. Therefore, from Figure 6a, the current stresses of S₁ and S₂ can be derived as

$$I_{S1,\mathit{stress}}=I_{S2,\mathit{stress}}=\frac{n}{1-{2D}_{\mathit{sw}1}}{I}_o.$$

(26)

In addition, from Figure 6b, it can be found that the current flowing through the switches S₁ and S₂ will pass the diodes of D₁ and D₂. Therefore, the current stresses of D₁ and D₂ can be expressed as

$$I_{D1,\mathit{stress}}=I_{D2,\mathit{stress}}=\frac{n}{1-{2D}_{\mathit{sw}1}}{I}_o.$$

(27)

The current stresses of S₃, S₄, S₅, and diode D₅ can be determined in SIDO mode, in which these components will endure the highest current stresses. As Figure 12a is referred to, the current stresses of S₃, S₅, and D₅ can be calculated as

$$I_{S3,\mathit{stress}}=I_{S5,\mathit{stress}}=I_{D5,\mathit{stress}}=\frac{-1+{2D}_{\mathit{sw}1}-{3D}_{\mathit{sw}3}+{2D}_{\mathit{sw}3}^2}{\left(-2+{2D}_{\mathit{sw}1}\right)D_{\mathit{sw}3}}{I}_o.$$

(28)

While referring to Figure 12b, it can be found that the switch S₄ endures the same current as that of switch S₅

$$I_{S4,\mathit{stress}}=\frac{-1+{2D}_{\mathit{sw}1}-{3D}_{\mathit{sw}3}+{2D}_{\mathit{sw}3}^2}{\left(-2+{2D}_{\mathit{sw}1}\right)D_{\mathit{sw}3}}{I}_o.$$

(29)

The remaining part of the current-stress determination is for diodes D₃ and D₄. For diode D₃, SISO-PV mode is applied. Based on Figure 6b, the current stress of diode D₃ can be accordingly calculated and given as

$$I_{D3,\mathit{stress}}=\frac{1}{1-D_{\mathit{sw}1}}{I}_o.$$

(30)

Meanwhile, DISO mode is applied and then, the current stress of diodes D₄ can be obtained. According to Figure 10d, this current stress is given below:

$$I_{D4,\mathit{stress}}=\frac{{\mathit{nD}}_{\mathit{sw}4}}{1-{2D}_{\mathit{sw}1}}{I}_o.$$

(31)

3.4. Inductance Design

There are two magnetic devices utilized in the MPMDC, which are L₁ and T_r. The inductance of L₁ and the magnetizing inductance of L_m both have to be in good design for achieving better features of converter operation. The T_r will be used in SISO-PV, DISO, and SIDO modes, among which the SISO-PV is the major mode for the design of T_r. That is, the L_m in T_r will carry the largest amount of current among all converter modes. Therefore, the inductance design of L_m is based on SISO-PV mode. To ensure that the L_m can be in continuous conduction mode (CCM) over all the five converter modes, the minimum of the magnetizing current, i_Lm,_min, is therefore estimated and expressed as

$$i_{\mathit{Lm},\mathit{min}}=I_{\mathit{Lm},\mathit{avg}}-\frac{\Delta i_{\mathit{Lm}}}{2}=\frac{{\mathit{nI}}_o}{1-{2D}_{\mathit{sw}1}}-\frac{V_{\mathit{pv}}{D}_{\mathit{sw}1}}{{2L}_m{f}_s}.$$

(32)

At the boundary conduction mode (BCM), i_Lm,min is set to be zero. Accordingly, the designed inductance of L_m has to be greater than the minimum inductance L_m,min for CCM operation. The L_m,min will be calculated as follows:

$$L_{m,\mathit{min}}=\frac{(1-D_{\mathit{sw}1})\left(1-{2D}_{\mathit{sw}1}\right)R_o}{{2n}^2{f}_s}.$$

(33)

For L₁ design, it will be used in the modes of SISO-battery, DISO, SIDO, and BF. The SISO-battery mode is the major mode because the L₁ will carry the largest amount of current in this mode. The minimum current of L₁, i_L1, can be derived as

$$i_{L1,\mathit{min}}=I_{L1,\mathit{avg}}-\frac{\Delta i_{L1}}{2}=\frac{V_{\mathit{bat}}{D}_{\mathit{sw}4}}{R{\left(1-D_{\mathit{sw}4}\right)}^2}-\frac{V_{\mathit{bat}}{D}_{\mathit{sw}4}T}{{2L}_1}.$$

(34)

At boundary condition, the i_{L1, min} is equal to zero. Then, calculating with (34) will yield the minimum value of L₁, L_1,min, to ensure the converter can be in CCM operation.

$$L_{1,\mathit{min}}=\frac{{\left(1-D_{\mathit{sw}4}\right)}^2{R}_o}{{2f}_s}.$$

(35)

3.5. Capacitance Design

How large the value of capacitance will affect the voltage fluctuation on a capacitor. The voltage variation of capacitor C₁, denoted as ΔV_C1, is determined by capacitor current i_C1, switching frequency f_s, and its capacitance. That is,

$$\Delta V_{C1}=\frac{i_{C1}\Delta t}{C_1},$$

(36)

in which capacitor current i_C1 can be estimated by

$$i_{C1}=\frac{1-{2D}_{\mathit{sw}1}}{{2\mathit{nD}}_{\mathit{sw}1}}{I}_o.$$

(37)

Therefore, the capacitance C₁ can be obtained as

$$C_1=\frac{\left(1-{2D}_{\mathit{sw}1}\right)I_o}{{2\mathit{nD}}_{\mathit{sw}1}\Delta V_{C1}{f}_s}.$$

(38)

From the above relationship, it can be realized that the smaller ΔV_C1 is required, the higher capacitance C₁ must be adopted. In addition, switch duty ratio D_sw1, switching frequency f_s, and the output current I_o will also influence the determination of the capacitance.

As for the other capacitor C_o, voltage fluctuation on it can be expressed as

$$\Delta V_{\mathit{Co}}=\frac{i_{\mathit{Co}}\Delta t}{C_o}.$$

(39)

Since the i_Co is equal to the output current I_o, capacitance C_o can thus be expressed as

$$C_o=\frac{I_o{D}_{\mathit{sw}1}}{\Delta V_{\mathit{Co}}{f}_s}.$$

(40)

The above relationship reveals that the capacitance C_o is inversely proportional to the voltage fluctuation on the output capacitor, ΔV_Co. In addition, output current I_o, the duty ratio of switch S₁, and switching frequency f_s will also dominate the determination of C_o, which is the same as the estimation of C₁.

4. Experimental Results

To verify the feasibility of the proposed MPMDC, a 200-W prototype is built and then tested. Figure 20 is the photograph of the prototype. The associated parameters and circuit components used in the main power stage are summarized in

Table 2. Circuit parameters and components used in the prototype.

Parameters	Values & Specifications
Pbus (DC-bus power)	200 W
Pbat (Battery power)	50 W
Vbus (DC-bus voltage)	200 V
Vpv (PV voltage)	24 V
Vbat (Battery voltage)	48 V
fs (Switch frequency)	50 kHz
L1 (Inductance)	300 μH
Lm (Magnetizing inductance)	270 μH
Lk (Leakage inductance)	3.6 μH
S1 and S2 (Power MOSFET)	IXTK90N25L2 (250 V/90 A)
S3, S4 and S5 (Power MOSFET)	IXFH36N50P (500 V/36 A)
D1 and D2 (Diodes)	DSSK 60-02A (200 V/2 × 30 A)
D3, D4 and D5 (Diodes)	DPG60C300HB (300 V/2 × 30 A)
C1 (Electrolytic capacitor)	3 × 10 μF
Co (Electrolytic capacitor)	100 μF
Cbat (Electrolytic capacitor)	68 μF
n (Transformer turns ratio)	43:65

. In converter control, all the parameters at the terminals of the converter are detected to determine which operation mode will be selected, as illustrated in Figure 21. Then, associated sub-control blocks are called for to determine control signals for the corresponding operation of a selected mode. There are three sub-control blocks, as shown in Figure 22, which are the sub-control block of PV power injection (SCPVPJ), the sub-control block of battery discharge (SCBD), and the sub-control block of battery charge (SCBC). The SCPVPJ is in charge of the control of drawing PV power with maximum power point tracking (MPPT) and then, exports the PV power to output by controlling the active switches S₁ and S₂. The SCBD is responsible for the determination of the control signals for switches S₄ and S₅ so that the proposed converter can perform battery discharging. Meanwhile, the SCBC is for switches S₃, S₄ and S₅ to fulfill the battery charging of the converter.

4.1. SISO-PV Mode

While the MPMDC works in SISO-PV mode and at full load, Figure 23 shows associated experimental measurements. Figure 23a is the switch voltage of S₁ and S₂, along with the corresponding control signals, in which the blocking voltage of both switches is around 160 V. Figure 23b is the measured current waveform of switches S₁ and S₂. The current waveform reveals that the average current of both switches is about 9.92 A, which is close to the theoretical result of 9.87 A calculated from (26). The leakage current is illustrated in Figure 23c. In addition, the average current of diodes D₁ and D₂ is presented in Figure 23d, which is calculated as 9.89 A, and this value approaches the theoretical estimation of (27). Similarly, the measured current of D₃ is given in Figure 23e, and its average is about 1.77 A, which meets the calculating result from (30).

4.2. SISO-Battery Mode

While the MPMDC works in SISO-Battery mode and at full load, Figure 24 shows the associated experimental measurements. Figure 24a is the switch voltage of S₄, along with the corresponding control signal, in which the blocking voltage of the switch is around 200 V. Figure 24b is the measured current waveform of switches S₄. This current waveform reveals that the average current of both switches is about 5.34 A. The inductor current i_L1 is illustrated in Figure 24c. In addition, from Figure 24d, since the switch current i_S5 is negative, the switch S₅ can be worked as a synchronous switch. In SISO-battery mode, the practical average current of S₅ is around 5.31 A.

4.3. DISO Mode

To demonstrate the converter in DISO-mode operation, associated key measurements at full load are illustrated in Figure 25. Figure 25a is the switch current of S₄ and its control signal, in which the switch current is measured to be around 3.02 A. In Figure 25b, the inductor current i_L1 increases or decreases linearly, which verifies that the voltage across inductor L₁ can be invariable during the periods of switch ON and switch OFF. That is, the capacitances adopted in the converter are valid for constant-voltage sustaining. Additionally, the i_L1 is negative, which proves that battery energy can be fed to the DC-bus. The diode currents of D₁ and D₂ are shown in Figure 25c, the average of which is measured as 4.23 A. This value is lower than that in Figure 25d, which confirms that the diodes D₁ and D₂ endure a maximum current in SISO-PV mode. The measured current of D₄ is also given in Figure 25d, and its average is about 3.11 A, which meets the calculating result from (31).

4.4. SIDO Mode

As for working in SIDO mode, Figure 26 is the related measurement of switch currents at full load. Figure 26a shows the switch current of S₃, from which it can be calculated that the average of this current is 3.21 A. This value is close to the theoretical estimation of 2.98 A according to (28). Figure 26b is the measured current waveform of S₁ and S₂, which reveals that the peak current of both switches is less than 10 A.

4.5. BF Mode

While in BF mode, Figure 27 illustrates the experimental voltage and current waveforms. The switch S₅ serves as the main switch, and its voltage along with the control signal is shown in Figure 27a. Meanwhile, Figure 27b is the measured current waveform of S₅, according to which the average current of S₅ can be found and about 1.22 A. The inductor current i_L1 is also measured and presented in Figure 27c, observed from which this current is always positive. That is, the DC bus charges the battery in this mode.

As for the demonstration of a sudden change from an operation mode to another mode, the mode change from SISO-battery to DISO is carried out and the voltages of DC bus, PV panels, and battery are measured, which are shown in Figure 28. In this case, the DC-bus requires a specific power of 200 W, and at the beginning, the battery supplies this 200-W loading. Then, PV panels begin to inject energy into the DC bus to share the power supply and will provide half of the load at the end. Accordingly, the providing power of the battery will drop to 100 W. Figure 28 illustrates that the converter can achieve system stability over the mode change. Figure 29 depicts the converter efficiency of the prototype from light load to full load. This measurement reveals that the DISO possesses higher efficiency than the other operation modes and its peak efficiency can be up to 94%. The converter efficiency will vary with which operation mode to select and how much power to be dealt with. Among the five operation modes, in terms of average efficiency from light load to full load, the converter will obtain the best efficiency in DISO mode and the worst in SIDO mode. The reason is that conduction losses dominate conversion efficiency. At a specific power, the PV port will carry a still higher current in SIDO than that in DISO, which results in lower efficiency in SIDO. The power budget of the converter in DISO mode and SIDO mode at rated power is illustrated in Figure 30 and Figure 31, respectively, from which it can be observed that switch losses and diode losses will dominate the converter efficiency. In DISO mode, switch losses and diode losses count for 26% and 47%, respectively. Meanwhile, in SIDO mode, count for 37% and 30%, respectively. To improve efficiency, a soft-switching mechanism and power semiconductor devices with better performance and low forward voltage can be considered.

5. Performance Comparison

The comparison of the proposed converter with other latest isolated three-port converters is summarized in

Table 3. Performance comparison between the proposed converter and other recently proposed topologies.

Ref.	[21]	[29]	[30]	[31]	Proposed
Input voltage	60 V	30 V	20–40 V	50 V	24 V
Battery voltage	72 V	24 V	60 V	50 V	48 V
Output voltage	200 V	400 V	760 V	100 V	200 V
Rated power	600 W	200 W	500 W	1000 W	200 W
MOSFETs	12	3	6	14	5
Diodes	0	3	4	0	5
Capacitors	3	6	8	1	3
Magnetic elements	5	4	3	2	2
Operational mode	4	3	2	2	5
Turns ratio (n)	2	5	2	2	1.5
Isolation	Yes	Yes	Yes	Yes	Yes
Leakage energy recycling	No	Yes	No	Yes	Yes
Voltage gain (bus voltage)	$V_{\mathit{pv}}\frac{n_2\left(D_2-D_4\right)}{1-D_2}+V_{\mathit{bat}}\frac{\frac{n_2}{1-n_1}{D}_4}{1-D_2}$	$V_{\mathit{pv}}\frac{n}{1-D_1}+V_{\mathit{bat}}\frac{{\mathit{nD}’}_2}{D_1}$	$\frac{V_{\mathit{pv}}}{D} \mathrm{or} {6\mathit{nV}}_{\mathit{bat}}$	$\frac{{\mathit{nR}}_L}{{2f}_s}\left[\frac{V_{\mathit{dc}1}{D}_{13}\left(1-D_{13}\right)}{L_{f1}}+\frac{V_{\mathit{dc}1}{D}_{23}\left(1-D_{23}\right)}{L_{f2}}\right]$	$V_{\mathit{pv}}\frac{{2\mathit{nD}}_1}{1-{2D}_1}+V_{\mathit{bat}}\frac{D_4}{1-D_4}$

. The comparison items mainly include the number of power switches, diodes, capacitors, magnetic elements, and operation modes. Besides, the ability of leakage-energy recycling, the turns ratio of the transformer, and converter specification are also listed. Table 3 shows that the obvious advantages of the MPMDC include: the feature of leakage-energy recycling, with the most diverse operation modes, the least number of magnetic components in addition to a minimum number of capacitors required, and no need for a high turn ratio of the transformer. Based on these advantages, the MPMDC is very suitable for green power processing.

6. Conclusions

A multi-port multi-directional converter is proposed, which can accomplish a variety of power flow controls to perfectly function clear-energy management in a single-stage structure. The converter operation modes can be up to five, which surpass other similar converters in power processing. In addition, the proposed converter possesses galvanic isolation and can achieve a high voltage-conversion ratio even only utilizing an inductor and a transformer. The energy stored in the leakage inductance of the transform can be recycled. To demonstrate the feasibility and verify the theoretical analysis of the converter, a 200-W prototype is built and then tested. From the measurements, it is confirmed that all the practical results can be consistent with the theoretical discussion and the converter is very suitable to deal with various clean-energy sources. At full-load conditions, the conversion efficiency of the converter in SISO-PV, SISO-battery, DISO, SIDO, and SISO are 85%, 88%, 91%, 84%, and 90%, respectively.