High-Performance Top-Gate Thin-Film Transistor with an Ultra-Thin Channel Layer

Abstract

Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO₂ TFTs, with a high field-effect mobility (μ_FE) of 136 cm²/Vs, a large on-current/off-current (I_ON/I_OFF) of 1.5 × 10⁸, and steep subthreshold slopes of 108 mV/dec. Here, μ_FE represents the maximum among the top-gate TFTs made on an amorphous SiO₂ substrate, with a maximum process temperature of ≤ 400 °C. In contrast to a bottom-gate device, a top-gate device is the standard structure for monolithic integrated circuits (ICs). Such a superb device integrity was achieved by using an ultra-thin SnO₂ channel layer of 4.5 nm and an HfO₂ gate dielectric with a 3 nm SiO₂ interfacial layer between the SnO₂ and HfO₂. The inserted SiO₂ layer is crucial for decreasing the charged defect scattering in the HfO₂ and HfO₂/SnO₂ interfaces to increase the mobility. Such high μ_FE, large I_ON, and low I_OFF top-gate SnO₂ devices with a coplanar structure are important for display, dynamic random-access memory, and monolithic three-dimensional ICs.

1. Introduction

The development of high-performance transistors has been continuously pursued for more than seven decades, since the transistor was invented in 1947. The metal-oxide thin-film transistor (TFT) was invented in 1964 [1], and had the important merits of low-temperature fabrication, a simple process for mass production, and visible light transparency [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26]. Moreover, metal-oxide TFTs have widely diverse applications, such as in active matrix organic light emitting diodes [2,3], flexible electronics [4,5,6,7], and gas sensors [8,9,10]. By applying a high-mobility channel material and high-dielectric-constant (high-κ) gate dielectric, metal-oxide TFT can also be used in high-speed low-power monolithic three-dimensional (3D) integrated circuits (ICs) [11,12,13,14,15,16]. Furthermore, the wide energy bandgap, excellent field-effect mobility (μ_FE) at high temperatures, and low leakage current of metal-oxide TFTs are especially important for high-temperature electronics [17] and dynamic random-access memory (DRAM) access transistors. In this paper, we report a top-gate SnO₂ TFT that uses a combined HfO₂ and SiO₂ stack as a gate dielectric layer and an SnO₂ channel layer. The top-gate TFT structure is more favorable than the bottom-gate device, owing to its high performance and easy integration in forming an IC. This top-gate device, with an SiO₂ interfacial layer between HfO₂ and SnO₂, exhibited an excellent device performance, with a remarkably high μ_FE of 136 cm²/Vs, a large on-/off-current (I_ON/I_OFF) of 1.5 × 10⁸, a sharp subthreshold slope (SS) of 108 mV/dec, and a much better resistance to moisture than the bottom-gate SnO₂ TFT. Here, the SiO₂ interfacial layer with a thickness of 3 nm is the key factor in decreasing the charged defect scattering inside HfO₂ and increasing the μ_FE. Such high-performance TFTs are crucial for future-generation high-resolution displays, DRAM access transistors, high interconnect-density monolithic 3D ICs, and 3D brain-mimicking ICs [11,12,13], where the down-scaling of silicon ICs is expected to be ended at an equivalent node around 1 nm within ten years.

2. Materials and Methods

P-type silicon wafers with ~10 ohmic-cm resistivity were used as substrates. A standard IC cleaning process was applied to remove the particles and native oxide from the silicon substrate. Then, an SiO₂ layer with a thickness of 300 nm was formed on the substrate, and was used as an inter-metal-dielectric layer of the IC. Thereafter, a 4.5 nm SnO₂ layer was deposited through reactive sputtering with a Sn target under a pressure of 7.6 × 10⁻³ torr, a mixture of O₂/Ar gas flow at 20/24 sccm, and a DC power of 50 W. The deposited SnO₂ layer was subjected to post-annealing at 350 °C in ambient air for 30 min. Next, 30 nm low work function aluminum Schottky source and drain electrodes [27,28] were deposited and patterned. Subsequently, a 3 nm SiO₂ layer and a 50 nm high-κ HfO₂ gate dielectric were deposited on the SnO₂ layer through physical vapor deposition. Finally, a 30 nm Ni top-gate electrode was created using electron-beam evaporation and patterning. The gate length and width are 50 and 400 μm, respectively. Material analyses through X-ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry (SIMS), and high-resolution transmission electron microscopy (TEM) were performed using Thermo Nexsa (Thermo Fisher Scientific Inc., Waltham, MA, USA), CAMECA IMS-6fE7 (CAMECA, Gennevilliers, France), and FEI Talos F200X (FEI company, Hillsboro, OR, USA), respectively. The electrical characterization of the device was measured using the HP4155B semiconductor parameter analyzer (HP, Englewood, CO, USA) and a probe station.

3. Results and Discussion

Figure 1a presents the drain-source current versus gate-source voltage (I_DS-V_GS) characteristics of the top-gate TFTs with and without the SiO₂ interfacial layer between the SnO₂ channel and the HfO₂ gate dielectric. The devices, with and without the ultra-thin SiO₂, exhibit good I_ON/I_OFFs of 1.5 × 10⁸ and 1 × 10⁸, respectively, and sharp turn-on SS values of 108 and 117 mV/dec, respectively. The interface trap density (D_it) can be calculated from SS [29,30]:

$$D_{it}=\frac{1}{q}\left(\frac{SS}{kT/q\times ln10}-1\right)C_{ox}-\frac{C_{dep}}{q},$$

(1)

where C_dep is the depletion capacitance. A D_it of 5.5 × 10¹² eV⁻¹cm⁻² is obtained, which is higher than the high-κ/silicon transistor. Further interface improvement can increase the SS and μ_FE.

Figure 1b depicts the μ_FE-V_GS characteristics of these devices. The μ_FE was obtained by a standard method used in silicon IC from the trans-conductance (g_m) at a small V_DS of 0.1 V:

$${\mu }_{FE}=\frac{g_m}{\left(W_G/L_G\right)C_{ox}{V}_{DS}},$$

(2)

where W_G, L_G, and C_ox are the gate width, gate length, and oxide capacitance, respectively. The C_ox was obtained from the measured C-V characteristics divided by the area of the Ni/HfO₂/SiO₂/Al MIM device on the same chip. The SnO₂ TFT with an SiO₂ interfacial layer has a μ_FE as high as 136 cm²/Vs, which is significantly higher than the 49.3 cm²/Vs for the device without the SiO₂ layer. This is the highest μ_FE value for top-gate TFTs made on an amorphous SiO₂ substrate and processed at a temperature of ≤ 400 °C [21,22,23,24,25].

To understand the significantly better the I_DS and μ_FE data for TFTs with an ultra-thin SiO₂ layer, we further measured the gate-source current versus gate-source voltage (I_GS-V_GS) characteristics. As shown in Figure 2a, the gate leakage current does not demonstrate a significant difference between these two devices because the interfacial SiO₂ layer was only 3 nm thick, and much thinner than the high-κ HfO₂, which had a thickness of 50 nm. The I_DS versus the drain-source voltage (I_DS-V_DS) characteristics are presented in Figure 2b. The TFT device with the ultra-thin SiO₂ layer exhibits a higher I_DS than the TFT without it, which is consistent with the I_DS-V_GS and μ_FE-V_GS data presented in Figure 1a,b, because the higher I_DS leads to a higher μ_FE value.

An XPS analysis was performed on both the HfO₂/SiO₂/SnO₂ and the HfO₂/SnO₂ stacks. Before the analysis, both samples were sputter-etched from HfO₂ to SnO₂ at a slow rate of 0.1 nm/s. As shown in Figure 3, the Sn 3d_5/2 spectrum of the SnO_x layer is split into three peaks: Sn⁴⁺, Sn²⁺, and Sn⁰. The binding energies of the Sn⁴⁺, Sn²⁺, and Sn⁰ peaks were 487, 486.5, and 485.2 eV, respectively. The intensity of Sn²⁺ is related to the p-type SnO TFT [18]. By contrast, Sn⁴⁺ conducts electrons for n-type TFTs [11,12,13,14,15,16]. As the results obtained using XPS analysis do not indicate obvious differences between these two samples, the inserted SiO₂ interfacial layer has little effect on the chemical composition of the SnO_x channel layer.

We further investigated the HfO₂/SiO₂/SnO₂ stack through TEM and SIMS measurements. Figure 4a displays the cross-sectional TEM image of the SnO₂ TFT with an SiO₂ interfacial layer, where the thicknesses of HfO₂, SiO₂, and SnO₂ were 50, 3, and 4.5 nm, respectively. The distributions of the Sn, Si, Hf, and O atoms in the gate stack and channel layer are depicted from the SIMS depth profiles in Figure 4b. An SiO₂ interfacial layer was clearly observed in both the TEM and SIMS analyses.

It is important to note that the extra SiO₂ interfacial layer will increase the thickness of the gate dielectric slightly and theoretically lead to a slightly higher transistor threshold voltage (V_TH) than the device without the SiO₂ layer. However, the I_DS-V_GS characteristics of the SnO₂ devices in Figure 1a display a contrary result. Thus, the increased V_TH for the device without the interfacial SiO₂ layer is due to the extra negative charges formed in HfO_2. These negative charges may also exist in the HfO₂/SnO₂ interface because the interface charges are strongly related to SS [22], which improves with the extra SiO₂ interfacial layer, as shown in Figure 1a. Further, such negative charges in the HfO₂ and HfO₂/SnO₂ interfaces can cause electron scattering and degrade the mobility [31,32], as shown in Figure 1b. It is known that the high-κ gate dielectric has defects, especially when formed at low temperatures. The negative charges formed in the HfO₂ and HfO₂/SnO₂ interfaces cause channel electron scattering and mobility degradation, which can be observed in the schematic diagrams illustrated in Figure 5a,b. The device with the SiO₂ interfacial layer has less negative charge scattering in HfO₂ and the interface because of the separation of the SiO₂ layer, which results in a higher mobility and I_DS.

The moisture degradation of TFT devices is a significant issue for an IC. Figure 6 illustrates the I_DS-V_GS characteristics for the as-fabricated top-gate coplanar and bottom-gate staggered SnO₂ TFTs in ambient air after 7 days and 30 days of exposure to air. The I_DS-V_GS characteristics of the bottom-gate SnO₂ TFT are shifted as high as 1.5 V after 7 days of exposure, and the I_OFF, SS, and I_ON further degrade significantly after 30 days of exposure to air. This is because the top SnO₂ layer can react with H₂O molecules in the air and form Sn-OH bonds [14,19,20], resulting in charged defects that lower the I_DS and μ_FE. The penetration of OH^- into the SnO₂ could also form defects and lead to a higher I_OFF by defect conduction [26]. In sharp contrast, only a slight V_TH shift of −0.09 V was observed in the top-gate device because the gate dielectric HfO₂ layer can behave as a passivation layer on the SnO₂ channel layer. The slight V_TH shift might be attributed to the intrinsic defects of the HfO₂ layer and the charge trapping and de-trapping phenomena of those defects [33,34].

In

Table 1. Important device performance comparison of various top-gate TFT devices on SiO₂ substrate.

Channel Materials	Channel Thickness (nm)	μFE (cm2/V·s) @VDS(V)	ION/IOFF	SS (mV/Decade)
a-Si [21]	100	0.9 @ 0.1	105	380
Poly-Si [22]	100	40 @ 0.1	1.5 × 106	310
IGZO [23]	40	11.44 @ 10	108	360
ZnO [24]	50	16.8 @ 0.1	2.4 × 109	102
SnO2 [25]	30	4.43 @ 1	4.19 × 106	300
SnO2 this work	4.5	136 @ 0.1	1.5 × 108	108

, we summarize the important device characteristics and compare them with the published data on top-gate TFTs made on amorphous SiO₂ substrates [21,22,23,24,25]. Our device with an ultra-thin channel thickness of 4.5 nm exhibits the highest μ_FE, a sharp SS for low-voltage operation, and a sufficiently large I_ON/I_OFF, which are crucial for display, low-leakage DRAM access transistors, and monolithic 3D IC applications. Further improvement of μ_FE and SS may be reachable by using a thicker SnO₂ layer than the 4.5 nm thickness and a Fin Field-Effect Transistor (FinFET) or gate-all-around structure, respectively.

4. Conclusions

An excellent device integrity was achieved for a top-gate TFT made on an amorphous SiO₂ substrate using a low process temperature of 350 °C with a high μ_FE of 136 cm²/Vs, a sharp SS of 108 mV/dec for low-voltage operations, and a sufficiently large I_ON/I_OFF of 1.5 × 10⁸. Such a top-gate structure is preferred for monolithic IC as compared to bottom-gate devices. In addition, a much better resistance to moisture can be achieved than in the bottom-gate device without passivation. Such a superb device performance is strongly related to the inserted ultra-thin SiO₂ layer between the HfO₂ and SnO₂. The outstanding device performance with top-gate structure is a crucial technology for future-generation high-resolution displays, low-leakage DRAM access transistors, and monolithic 3D brain-mimicking ICs.