Design of an Optimal Adoptive Fault Ride through Scheme for Overcurrent Protection of Grid-Forming Inverter-Based Resources under Symmetrical Faults

Abstract

As the integration of inverter-based resources (IBRs) is rapidly increasing in regard to the existing power system, switching from grid-following (GFL) to grid-forming (GFM) inverter control is the solution to maintain grid resilience. However, additional overcurrent protection, especially during fault transition, is required due to limited overcurrent capability and the high magnitude of spikes during fault recovery in IBRs, specifically in the GFM control mode. Furthermore, the power system stability should not be compromised by the employment of additional fault ride through (FRT) schemes. This article presents the design and implementation of an adoptive fault ride through (FRT) scheme for grid-forming inverters under symmetrical fault conditions. The proposed adoptive FRT scheme is comprised of two cascaded power electronic-based circuits, i.e., fault current ride through and a spikes reactor. This adoptive FRT scheme optimizes the fault variables during the fault time and suppresses the fault clearing spikes, without affecting system stability. A three-bus inverter-based grid-forming model is used in MATLAB/Simulink for the implementation of the proposed scheme. Further, a conventionally used FRT scheme, which includes fault current reactors, is simulated in the same test environment for justification of the proposed adoptive scheme. The adoptive FRT scheme is simulated for both time domain and frequency domain to analyze the response of harmonic distortion with the suppression of the fault current. Moreover, the proposed scheme is also simulated under the GFL mode of IBRs to justify the reliability of the scheme. The overall simulation results and performance evaluation indices authenticate the optimal, fault tolerant, harmonic, and spike-free behavior of the proposed scheme at both the AC and DC side of the grid-forming inverters.

1. Introduction

The history of past decades reveals that the affinity for renewable energy resources (RERs), such as wind and solar photovoltaic (PV) power, are increasing continuously due to the fast depletion of fossil-based energy resources and their negative contribution to global climate change [1,2]. Thus, the influence of inverter-based resources (IBRs) is expanding exponentially in the existing power system, specifically in Europe [3]. These IBRs are injecting power as a current source to the synchronous generators (SGs) dominant grid by maintaining stability and synchronism at the point of common coupling (PCC) using a phase-locked loop (PLL), which is categorized as a grid-following (GFL) mode. However, currently, the traditional power system may have been dominated by IBRs areas in developed countries. In such a scenario, the GFL mode is not a suitable option because it results in a decrease in overall system inertia and different fault current characteristics between SGs and IBRs, making them more prone to the loss of synchronism and instability [4]. Therefore, by taking advantage of the early awareness, the researchers and engineers are trying to change the operation mode of IBRs from the GFL mode to the grid-forming (GFM) mode [5]. Such an IBRs operation mode can create its own instantaneous AC voltage with the provided amplitude and frequency at the PCC.

Traditional electrical power generating units, such as synchronous generators, have high overcurrent capability—approximately 7 times that of the rated current due to its high inertia. In contrast, IBRs having electronic switches can additionally afford only 0.2 to 0.5 times the capability of the rated current in dynamic conditions [6]. Thus, an efficient strategy which can limit the high fault level and spikes within the affordable range of IBRs is required. As IBRs in the GFL mode behave as a current source, the protection during the fault and load change can be accomplished by current referencing because the output power is directly dependent on the reference value of the current. Moreover, this voltage phase-angle remains synchronized with the grid at the PCC due to PLL control [7]. Therefore, the current referencing technique is not a suitable solution for the GFM mode of inverters under severe fault conditions due to the limited current withstanding capability of the IBRs-based system, which shows instability, especially during fault recovery [8].

Thus far, various control strategies have been developed to operate IBRs in the GFM mode, such as a virtual synchronous generator (VSG), droop control, virtual oscillator control, and synchronous power control [9,10,11,12]. Each of these strategies have their own unique capabilities, but among these strategies, VSG and droop control are adopted for most case studies due to their small-signal stability due to their virtual impedance under normal conditions [13,14,15]. However, in the aforementioned strategies, the protection of IBRs based resources has not been considered for overcurrent or temporary voltage sag.

Considering the protection of IBRs, a simple method is to enhance the withstanding capacity of IBRs at the level of SGs to withstand high fault current. However, this is not an economically feasible technique. So far, different control-based and electronic-based fault ride through (FRT) schemes have been developed for the GFL mode that can effectively optimize the grid-tied distributed energy resources according to the latest grid codes [16,17,18,19]. For example, a bridge-type fault current limiter has been designed to optimally enhance the voltage sag during temporary faults for grid-tied PV systems [16]. Similarly, control schemes, such as the use of a fuzzy-logic based gradient descent controller, have been proposed to protect the IBRs and enhance the grid resilience of the grid-tied IBRs during abnormal conditions [17]. Additionally, in the case of multilevel inverter- (MLC) based IBRS, the reliable five-level inverter topology, the hybrid control strategy which unites the nearest level control with PWM and a modulation-based scheme for withstanding open circuit fault due to failure of a switch [20,21,22], has also been proposed. The mentioned FRT schemes works efficiently in the GFL mode due to the low severity of the fault surges at the moment of fault recovery. This is due to the fault current contribution, with a strong leading grid and a PLL structure that tightly maintains the phase angle.

However, in the case of the emerging GFM mode, the overcurrent protection has been proposed using different control algorithms. One of these is to change the control mode from GFM to GFL during fault conditions [23]. Still, this method has the limitation of grid existence and the wind-up problem that the integrator may be dangerous during symmetrical fault recovery [24]. Another solution is employing virtual impedance during fault time to decrease the nominal voltage of the inverter [25,26,27]. This can limit the fault current, but when the short-circuit ratio is altered, the overall effectiveness of the system is reduced. Moreover, the transient performance becomes severe when the virtual impedance alters abruptly during fault transitions [28]. Additionally, the most popular technique to limit the current under the limits of the IBRs is current referencing; however, this technique results in instability during large disturbances [8]. Apart from the mentioned scenarios, these techniques can restrict the fault current and enhance the voltage sag, but these methods result in high spikes during fault recovery, which may exceed the bearing capacity of electronic switches of the IBRs.

Instead of control based FRT strategies, this paper presents an adoptive electronic-based FRT scheme to restrict the fault current and enhance the voltage sag to near nominal IBRs values in the GFM mode. Additionally, the proposed scheme can resolve the severity of transient performance at the instant of fault clearance with the adaptation of instantaneous spikes reactor circuitry. The main contributions of this paper are given below.

• An electronic-based adoptive FRT scheme is designed for the optimization of fault parameters and the restriction of high spikes during fault transition at both the AC and DC sides of the inverters.
• The benchmarked three-bus test system, energized with grid-forming IBRs, is used for the implementation of the proposed FRT scheme under a bolted symmetrical fault.
• The simulation analysis of a conventionally used electronic-based FRT strategy, such as Crowbar, is carried out in the same test environment for comparative analysis to justify the effectiveness of the designed scheme.
• The total harmonic distortion (THD) under abnormal conditions is also calculated to analyze the performance of the designed scheme in the frequency domain.
• Additionally, the error for the fundamental parameters is calculated numerically to verify the performance of the designed FRT scheme in comparison to the conventional strategy with the help of mathematical formulations, such as integral square error (ISE), integral of time-weighted absolute error (ITAE), and integral absolute error (IAE).

The remaining sections of the article are structured as follows: Section 2 discusses the proposed test system and its control, Section 3 presents the design of the FRT schemes, Section 4 demonstrates the results and provides a discussion, and Section 5 offers the paper’s conclusion.

2. Proposed Grid Forming Model

In the future, transmission lines will be energized through grid forming IBRs with different capacities and locations. For such a scenario, a detailed MATLAB/Simulink three-bus GFM model, developed by the MIGRATE project, as illustrated in Figure 1, is used for the implementation of the designed electronic-based FRT scheme under the methods of [29].

Three voltage source converters of different power ratings, i.e., 250 MW, 500 MW, and 1000 MW, controlled with the GFM mode, are employed. Additionally, each source block consists of a DC source which can be fed by any renewable resource, such as a wind or solar PV generator, a three-phase inverter, an LCL filter, and GFM control structure.

These IBRs in the GFM mode are meshed through three transmission lines: T₁₂, T₁₃, and T₂₃ with lengths of 25 km, 50 km, and 125 km, respectively. A resistive load of 1125 MW is shared by the sources through droop control, according to their power ratings. To reduce the system complexity, the application of a fundamental renewable energy source, such as a PV panel and boost converter, are bypassed by the employment of a direct DC source as an input for the inverter. A three-phase, two level voltage source is adapted due to its low harmonics output and its simple application, as it possesses dual voltage and current control capability [30]. In order to deliver ripple free and smooth electrical parameters to the AC circuit, an LCL filter is used, and its values are shown in

Table A1. Test model rated parameters.

Parameters	VALUES
DC link voltage (Vdc)	640 kV
Rated power of the three sources	250 MW, 500 MW, 1000 MW
Nominal power factor	0.957
Rated phase to phase voltage (AC)	320 KV
Operating frequency	50 Hz
Load power	1125 MW
Switching frequency (inverter)	4 kHz
L-C-L filter (p.u)	0.005 H, 0.15 F, 0.066 H
P-F droop (${\mathrm{m}}_{\mathrm{p}}$)	0.02
Q-V droop (${\mathrm{n}}_q$)	$1{\mathrm{e}}^{-4}$ p.u
Cut-off frequency $\left({\mathsf{\omega }}_c\right)$	31.4 rad/s

of Appendix A, including the overall system parameters.

Grid Forming Control

The conventional GFM control structure is employed for each inverter, which is cascaded by three basic control blocks as the primary control, voltage control, and current control [31], as shown in Figure 2.

Further, these control blocks receive the uncontrolled variables in a d-q reference frame and deliver it in a controlled form for PWM generation in the abc frame, for the sake of simple and fast calculations, by using Clarke and Park transforms, as seen in Equations (1) and (2).

$$\left[\begin{array}{c}{\mathrm{v}}_{\mathrm{d}}\\ {\mathrm{v}}_{\mathrm{q}}\end{array}\right]=\frac{2}{3}\left[\begin{array}{c}\begin{array}{ccc}\cos \mathsf{\omega }\mathsf{\tau }& \cos \left(\mathsf{\omega }\mathsf{\tau }-\frac{2\mathsf{\pi }}{3}\right)& \cos \left(\mathsf{\omega }\mathsf{\tau }+\frac{2\mathsf{\pi }}{3}\right)\\ -\sin \mathsf{\omega }\mathsf{\tau }& -\sin \left(\mathsf{\omega }\mathsf{\tau }-\frac{2\mathsf{\pi }}{3}\right)& -\sin \left(\mathsf{\omega }\mathsf{\tau }+\frac{2\mathsf{\pi }}{3}\right)\end{array}\\ \begin{array}{ccc}1/2 & 1/2& 1/2\end{array}\end{array}\right]\left[\begin{array}{c}{\mathrm{V}}_{\mathrm{a}}\\ {\mathrm{V}}_{\mathrm{b}}\\ {\mathrm{V}}_{\mathrm{c}}\end{array}\right]$$

(1)

$$\left[\begin{array}{c}{\mathrm{i}}_{\mathrm{d}}\\ {\mathrm{i}}_{\mathrm{q}}\end{array}\right]=\frac{2}{3}\left[\begin{array}{c}\begin{array}{ccc}\cos \mathsf{\omega }\mathsf{\tau }& \cos \left(\mathsf{\omega }\mathsf{\tau }-\frac{2\mathsf{\pi }}{3}\right)& \cos \left(\mathsf{\omega }\mathsf{\tau }+\frac{2\mathsf{\pi }}{3}\right)\\ -\sin \mathsf{\omega }\mathsf{\tau }& -\sin \left(\mathsf{\omega }\mathsf{\tau }-\frac{2\mathsf{\pi }}{3}\right)& -\sin \left(\mathsf{\omega }\mathsf{\tau }+\frac{2\mathsf{\pi }}{3}\right)\end{array}\\ \begin{array}{ccc}1/2 & 1/2& 1/2\end{array}\end{array}\right]\left[\begin{array}{c}{\mathrm{i}}_{\mathrm{a}}\\ {\mathrm{i}}_{\mathrm{b}}\\ {\mathrm{i}}_{\mathrm{c}}\end{array}\right]$$

(2)

The dual voltage and current control loops are used to enhance power quality. However, the error compensation of the active and reactive components of the voltage and current in the d-q frame is guaranteed by the proportional-integral (PI), with feed-forward decoupling in both loops. The classical transfer function of the PI controller is illustrated, with different gains for the voltage and current loops, by Equations (3) and (4), respectively.

$${\mathrm{G}}_{\mathrm{PIv}}\left(\mathrm{s}\right)={\mathrm{K}}_{\mathrm{pv}}+{\mathrm{K}}_{\mathrm{iv}}\left(\frac{1}{\mathrm{s}}\right)$$

(3)

$${\mathrm{G}}_{\mathrm{PIc}}\left(\mathrm{s}\right)={\mathrm{K}}_{\mathrm{pc}}+{\mathrm{K}}_{\mathrm{ic}}\left(\frac{1}{s}\right)$$

(4)

where ${\mathrm{K}}_{\mathrm{pv}}$ and ${\mathrm{K}}_{\mathrm{pc}}$ are the proportional gains of the voltage and current loop, respectively. similarly, ${\mathrm{K}}_{\mathrm{iv}}$ and ${\mathrm{K}}_{\mathrm{ic}}$ are the integral gains for both loops.

The modulated voltage signal is generated by the voltage-reactive power droop through the control loops. However, the angle ${\theta }_{VSC}$ is generated by the frequency–real power droop to be used for switching signal through inverse Clarke and Park transforms.

The mentioned droop objectives are obtained by primary control using the following expressions.

$${\mathsf{\omega }}_{VSC}={\mathrm{m}}_{\mathrm{p}}\times \mathrm{LPF}\left(\mathrm{P}-{\mathrm{P}}^{*}\right)+{\mathsf{\omega }}_{set}$$

(5)

$$e^{*}{}_{gd}={\mathrm{n}}_{\mathrm{q}}\times \mathrm{LPF}\left(\mathrm{Q}-{\mathrm{Q}}^{*}\right)+{\mathrm{e}}_{set}$$

(6)

Here ${\mathrm{m}}_{\mathrm{p}}$ and ${\mathrm{n}}_{\mathrm{q}}$ are the active and reactive power droop gains, respectively, whereas ${\mathsf{\omega }}_{VSC}$ is the output frequency for the voltage source inverter. The droop gains, i.e., ${\mathrm{m}}_{\mathrm{p}}$ and ${\mathrm{n}}_{\mathrm{q}}$, can be determined after analyzing the simulated regulations characteristics of the frequency and output voltage of each source, operating in parallel, from no load to full load. The active droop gain can be determined by the ratio of the change in frequency to the change in real power; however, the reactive droop gain is calculated by the rate of change in voltage with respect to reactive power, as shown by Equations (7) and (8) below.

$${\mathrm{m}}_{\mathrm{p}}=\left( \frac{{\mathsf{\omega }}_{\mathrm{NL}}-{\mathsf{\omega }}_{\mathrm{FL}}}{{\mathrm{P}}_{\mathrm{NL}}-{\mathrm{P}}_{\mathrm{FL}}} \right)$$

(7)

$${\mathrm{n}}_{\mathrm{q}}=\left( \frac{{\mathrm{V}}_{\mathrm{NL}}-{\mathrm{V}}_{\mathrm{FL}}}{{\mathrm{Q}}_{\mathrm{NL}}-{\mathrm{Q}}_{\mathrm{FL}}} \right)$$

(8)

Here, the subscripts $\mathrm{NL}$ and $\mathrm{FL}$ denote no-load and full-load, respectively.

Additionally, the low-pass filter ($\mathrm{PLF}$) in the Equation (9) is used for filtering measurement noises [32,33].

$$\mathrm{LPF}=\left(\frac{{\mathsf{\omega }}_c}{{\mathsf{\omega }}_c+s}\right)$$

(9)

Here, ${\mathsf{\omega }}_c$ is the cut-off frequency [34].

3. Design of Fault Ride through Scheme

To maintain the high magnitude of current under abnormal conditions within the limit of the overcurrent capacity of IBRs in the GFM mode, i.e.,1.2 to 1.5 p.u [35], various control-based strategies has been designed. However, these strategies, as discussed in the literature section, do not provide protection against high current spikes caused by the forced retardation of energy during the fault recovery. The frequently adopted current referencing technique using limiting function is employed in the grid-forming 3-bus test model. The current referencing technique is to limit the fault current to 1.2 p.u of the rated current. However, this technique causes transient instability and harmonic distortions when the system is slightly disturbed when it is already operating at its maximum power transfer capability, or the current limiter is saturated [8]. When the system is operating below its maximum power capability, i.e., the power angle “σ” is less than 90°, it may be considered stable, depending upon the margin of stability, but it will cause harmonic distortions during fault time and high spikes during fault transition, as occurred in our test case. This unfavorable behavior of the current referencing technique is due to the absence of any physically passive component to dissipate the excessive restricted energy. The working principle of current reference limiting is given by the Expression (10) below.

$$I=\left\{\begin{array}{c}I, if \sqrt{I_R^2+I_X^2}<I_{max} \\ I\times \frac{I_{max}}{\sqrt{I_R^2+I_X^2}} , else \end{array}\right\}$$

(10)

Here $“I_{max}”$ is the limiting value, “I” is load current, $I_R$ is the resistive component, and $I_X$ is the reactive component of the load current, respectively. The conditions of the working principle in Equation (10) clearly show that the limiter only works under saturated conditions, i.e., when the magnitude of the current is higher than the limiting value. Under saturated conditions, the phase angle of the current remains constant, and that angle is the critical angle of stability, i.e., any further disturbance in the system leads toward instability and harmonic distortions.

Therefore, an electronic-base adoptive FRT scheme is proposed that aims to protect IBRs during overcurrent and transient periods. The proposed FRT scheme optimizes the fault current by involving the passive and active components in the transmission line to dissipate the fault energy by compensating the bolted fault impedance to the rated impedance of the system. Thus, the proposed scheme does not lead the system towards saturation and acts as voltage source; hence, the power-angle characteristics equation satisfies this case. For comparative analysis, the latest electronic-based FRT circuitry parallel-resonance fault current limiter (PRFCL) is also implemented in the same test environment for the justification of the optimal response of the proposed scheme [36]. Its circuit diagram is shown in Figure 3A below.

3.1. Adoptive FRT Scheme

The protection of IBRs from high spikes in the grid-forming mode is essential to be address, as it can severely damage the current-sensitive electronic switches of the IBRs during large disturbances, such as symmetrical faults. Previously, most of the overcurrent protection of the grid-forming inverters has been conducted through software-based controllers [37]. Similarly, various electronic-based FRT strategies have been presented to restrict the overcurrent within the limit of the IBRs’ capacity, but these strategies lack protection against transitional surges during fault recovery [38,39].

Therefore, to achieve optimized and harmonic free output response, an adoptive electronic-based FRT scheme is proposed, as depicted by Figure 3. The technical logic used to adapt the proposed scheme is an instantaneous FRT circuitry cascaded with the PRFCL recently designed for a wind farm-fed grid to mitigation of spikes at fault recovery time. The design of the adoptive FRT scheme is the extension of PRFCL, shown in block A, by linking an additional circuitry, i.e., a spikes reactor, as shown in block B. The PRFCL and the spike ride through circuitries successively actuate during the fault and fault recovery time to keep the fault current within the limit of the IBRs’ overcurrent capacity. Each block of the proposed adoptive FRT scheme provides two paths for the power flow: one for normal conditions and another for fault conditions, as shown below.

3.1.1. Fault Current Ride through (Block A)

Bridge path: This path is comprised of four diodes (D₁ to D₄) forming a bridge with a controlled power electronic switch and a small valued current limiting reactor (${\mathrm{L}}_{\mathrm{dc}}$) in shunt with a free-wheeling diode D_f.

Resonance path: During abnormal conditions, the resonance path, consisting of a capacitor (${\mathrm{C}}_{\mathrm{A}}$) and an inductor (${\mathrm{L}}_{\mathrm{A}}$), resonate in parallel with the system nominal frequency. Moreover, an ohmic resistance (${\mathrm{R}}_{\mathrm{A}}$) is added in series with the capacitor to eliminate the fluctuating ripples.

The current limiting reactor (${\mathrm{L}}_{\mathrm{dc}}$) is used in the bridge path to protect the four inter-bridge diodes from the small switching surges, i.e., $\raisebox{1ex}{$\mathrm{di}$}\!\left/ \!\raisebox{-1ex}{$\mathrm{dt}$}\right.$, and its value can be selected according to the power rating of the diodes. The detailed mathematical modeling of the components used in block A is elaborated by the authors of [36].

3.1.2. Spikes Reactor (Block B)

The spikes reactor block for spikes elimination is comprised of the same bridge path for normal conditions as that for fault current ride through. However, during the fault recovery process, the spikes path in the spikes reactor block, consisting of an inductive reactor with a small resistance in series, is used to suppress the high magnitude of the current.

The concept behind the mathematical design of the adoptive FRT scheme is such that the impedance of the fault path must be the same as that of the load impedance and should be resonating with the system frequency. The equivalent impedance of block A can be derived by Equation (11) as:

$${\mathrm{Z}}_{\mathrm{eqA}}=({\mathrm{R}}_{\mathrm{A}}-\mathrm{j}/\mathsf{\omega }{\mathrm{C}}_{\mathrm{A}})\Vert \mathrm{j}\mathsf{\omega }{\mathrm{L}}_{\mathrm{A}}={\mathrm{L}}_{\mathrm{A}}/{\mathrm{C}}_{\mathrm{A}}{\mathrm{R}}_{\mathrm{A}}+\mathrm{j}\mathsf{\omega }{\mathrm{L}}_{\mathrm{A}}$$

(11)

Although there may be various possible values of ${\mathrm{C}}_{\mathrm{A}}$ and ${\mathrm{L}}_{\mathrm{A}}$ with which the system can resonate, the one with the best response and the lowest ohmic resistance is selected to protect the circuit from the heat effect. Considering this, the equivalent impedance of the spikes path as shown by Figure 3B is derived from Equation (12) for each phase.

$${\mathrm{Z}}_{\mathrm{eqB}}={\mathrm{R}}_{\mathrm{B}}+\mathrm{j}\mathsf{\omega }{\mathrm{L}}_{\mathrm{B}}$$

(12)

To select the optimal values of ${\mathrm{R}}_{\mathrm{B}}$ and ${\mathrm{L}}_{\mathrm{B}}$ for smooth operation during fault recovery, the spikes reactor circuit should utilize the power of the line equal to the normal carrying power, and Equations (13) and (14) give the power at normal and abnormal conditions, respectively.

$${\mathrm{P}}_{\mathrm{spike} \mathrm{reactor}}\le {\mathrm{P}}_{\mathrm{gen}}$$

(13)

$${\mathrm{P}}_{\mathrm{spike} \mathrm{reactor}}=\frac{{\mathrm{V}}_{\mathrm{PCC}}^2{\mathrm{R}}_{\mathrm{B}}}{{\mathrm{R}}_{\mathrm{B}}^2+{\mathrm{X}}_{\mathrm{B}}^2}$$

(14)

Here, ${\mathrm{P}}_{\mathrm{gen}}$, ${\mathrm{V}}_{\mathrm{PCC}}$, and ${\mathrm{X}}_{\mathrm{B}}$ are the generated power, the PCC voltage, and the shunt inductance, respectively. Thus, by solving Equations (13) and (14), the inequality yields ${\mathrm{R}}_{\mathrm{B}}$.

$${\mathrm{R}}_{\mathrm{B}}\ge \frac{{\mathrm{V}}_{\mathrm{PCC}}^2+\sqrt{{\mathrm{V}}_{\mathrm{PCC}}^4-{\mathrm{P}}_{\mathrm{gen}}^2{\mathrm{X}}_{\mathrm{B}}^2}}{{\mathrm{P}}_{\mathrm{gen}}}$$

(15)

Additionally, ${\mathrm{R}}_{\mathrm{shB}}$ is a positive real value, so the term inside the square root must be positive as

$${\mathrm{V}}_{\mathrm{PCC}}^4-{\mathrm{P}}_{\mathrm{gen}}^2{\mathrm{X}}_{\mathrm{B}}^2\ge 0$$

(16)

Solving Equation (16) for ${\mathrm{X}}_{\mathrm{B}}$, we get

$${\mathrm{X}}_{\mathrm{B}}\le \frac{{\mathrm{V}}_{\mathrm{PCC}}^2}{{\mathrm{P}}_{\mathrm{gen}}}$$

Thus, the values of ${\mathrm{R}}_{\mathrm{B}}$ and ${\mathrm{L}}_{\mathrm{B}}$ can be selected under the above-mentioned constraints for a smooth and harmonic-free response of output variables. All the parameter values of the proposed scheme are mentioned in

Table A2. Controller and FRT constants.

	Parameters	Values
PI (voltage loop)	$k_{pv}$	0.52
	$k_{iv}$	1.16
PI (current loop)	$k_{pc}$	0.738
	$k_{ic}$	1.19
Adoptive FRT	${\mathrm{L}}_{\mathrm{A}}$	$2.5{\mathrm{e}}^{-2} \mathrm{H}$
	${\mathrm{R}}_{\mathrm{A}}$	$87 \Omega$
	${\mathrm{C}}_{\mathrm{A}}$	$1{\mathrm{e}}^{-3} \mathrm{F}$
	${\mathrm{L}}_{\mathrm{dc}}$	0.001 $\mathrm{H}$
	${\mathrm{L}}_{\mathrm{B}}$	$2.2{\mathrm{e}}^{-2} \mathrm{H}$
	${\mathrm{R}}_{\mathrm{B}}$	$80 \Omega$

of Appendix A. The proposed adoptive FRT scheme is designed to yield the optimal response of the electrical variables at the fault time, as well as during fault recovery. However, this scheme is prone to higher switching losses due the interconnection of additional bridge path of the four diodes. Therefore, the diodes with soft switching operation are recommended to minimize these losses.

4. Results and Discussion

The behavior of output variable grid-forming IBRs under large disturbance are analyzed with the proposed adoptive FRT scheme in both the time and frequency domain using MATLAB/Simulink. Furthermore, the deviations from the reference values are calculated using the performance evaluation indices. The previously designed FRT, i.e., the PRFCL response, is also carried out in the same test environment for the justification of the better response of the adoptive FRT scheme during severe symmetrical fault. The limited, stable, and harmonic-free responses of the variable are verified using the three mentioned techniques at both the AC and DC side of the per-unit three-bus test system in the GFM mode.

4.1. Time Domain Response

4.1.1. DC Side Parameter Response

The comparative analysis of the proposed adoptive FRT scheme to enhance the voltage sag without compromising the high magnitude of the fault transitional surges is carried out in the time domain under a large disturbance. To provide such an analytical environment, a severe three-phase symmetrical fault is applied at the AC side of the system for 0.5 s.

The response of the DC source output, i.e., the DC link voltage (Vdc) and DC current (Idc) is considered as the main influential unit of the inverter-based system. Thus, any disturbance on the AC side will show its impacts on the DC side as well. The output response of the three DC sources in regard to droop power share with different power ratings, i.e., 250 MW, 500 MW, and 1000 MW, are shown in Figure 4. It can be clearly analyzed from Figure 4a–c, for DC link voltage, and Figure 4d–f, for its corresponding current responses, that the proposed adoptive FRT scheme can effectively minimize the high spikes. The GFM inverters behaves as a voltage source for the Vdc is maintained at its nominal value by controlling its current, i.e., Idc, according to the output power at the AC side. However, the Vdc is maintained as constant, but it gives voltage spikes during fault transition, which are significantly minimized using the adoptive FRT scheme as compared to the conventional FRT strategy, as shown in Figure 4a–c. Similarly, the DC current is retained with both schemes in order to meet the load at the AC side, as the fault impedance is enhanced to the load impedance through the presented FRT schemes. Again, the proposed scheme responds with negligible spikes and minimum settling time during the fault recovery for Idc, as illustrated in Figure 4d–f. This authenticates the proposed adoptive FRT scheme as efficient, robust, and fault tolerant at the DC side of the GFM network as well.

Additionally, three various performance evaluation indices are used to investigate the deviation of the measured values from the reference values for the DC source, i.e., source_1. These evaluation indices are the mathematical techniques which calculate the error magnitude, which are tabulated in the

Table 1. Performance evaluation of intended FRT schemes for DC parameters.

Evaluated Schemes	Vdc			Idc
	IAE	ISE	ITAE	IAE	ISE	ITAE
Without FRT	0.1432	0.0436	0.0213	1.926	1.0802	0.9415
With FRT	0.1058	0.0313	0.0071	0.160	0.0473	0.0271
With adoptive FRT	0.0836	0.0212	0.0052	0.091	0.0075	0.0122

, for three different tested schemes. These indices define the efficiency of a system as high if its value is minimum. Therefore, this analysis also verifies the efficient performance of adoptive scheme for the DC parameters as compared to the conventional FRT scheme.

4.1.2. AC Side Parameter Response

The variables response on the AC side limits the fault impedance to zero due to the bolted symmetrical fault imposed for 0.5 s. Therefore, the fault current tends to be infinity, but due to the current limitation setting, i.e., 1.2 p.u, the AC side parameters produce high spikes during fault recovery because of this forced limitation. The voltage sag is also limited, as it does not fall to zero, unlike its behavior in the three phase faults due to current referencing, as shown without the FRT scheme. However, by using the traditional FRT strategy, the current can be restricted to near nominal value, but this strategy has no setup to optimize the severe fault switching surges which are higher than the IBRs’ withstanding limit. However, the adoptive FRT scheme normalizes the fault current with negligible spikes, as depicted in Figure 5a–c. Likewise, the voltage response is the reflection of the current at each bus, which also authenticates the optimal and spikes free behavior of the adoptive FRT scheme, as shown by Figure 5d–f.

Moreover, the performance evaluation indices numerically justify the low error of the proposed adoptive scheme, as shown by

Table 2. Performance evaluation of intended FRT schemes for AC voltage and current at the PCC.

Evaluated Schemes	Vac			Iac
	IAE	ISE	ITAE	IAE	ISE	ITAE
Without FRT	1.1032	0.8416	0.6720	1.125	0.8022	0.7041
With FRT	0.1253	0.0260	0.0061	0.141	0.0353	0.0172
With adoptive FRT	0.0721	0.0182	0.0034	0.085	0.0259	0.0108

. These analyses are carried out at the PCC, which accumulates the combined effect of the three sources.

The corresponding real and reactive output power of the three sources are given in Figure 6 below. The real output power becomes zero, and the reactive power rises during the three phase faults without any FRT scheme, as expected. However, with the FRT scheme, these variables regained their nominal values, but produce high spikes which are out of the limit of IBRs’ overcurrent capability. These spikes are minimized to an acceptable limit with the adoptive FRT scheme, as it incorporates an instantaneous FRT setup for spikes limitation. The effectiveness of the proposed scheme is equally justified for the three droop shared power sources as compared to the traditional scheme. The fault recovery duration is zoomed out at the real power component for more clarification of the magnitude and settling time of the oscillations, shown in Figure 6a–c below.

According to the German frequency requirements presented by E.ON (Energy On), the frequency should not exceed the range of 49.5–50.5 Hz for distributed energy sources during the contingencies in order to remain connected to the AC network [40]. As per frequency response during severe fault, the limit of frequency is exceeding the acceptable limits at each bus, as shown by Figure 7. The frequency at each bus is limited to the allowable range, but here again, the traditional FRT was compromised in regard to switching transients. However, the proposed adoptive FRT scheme can also optimize the switching surges to near the rated value and with minimum settling time.

4.2. Total Harmonic Distortions (THD) Analysis

The effectiveness of the proposed adoptive scheme in terms of optimal response is verified in the time domain. However, the quality of the AC signals should not be compromised by the involvement of any circuitry. In order to see the impact of the proposed electronic based FRT scheme on harmonic distortions in the AC current and voltage waveforms during the fault and fault recovery time, the fast Fourier transform (FFT) analysis tool in MATLAB/Simulink is used. Only the fault duration is used for the investigation of THD in which the FRT schemes are contributing. It is found that the AC waveform, without the FRT scheme, gives a high THD in the percentage of fundamental values during symmetrical faults, which are 54.4% and 601% for current and voltage, respectively, as shown by Figure 8. The reason for the unexpectedly high THD without using the FRT scheme is due to the built-in current referencing limiter in the GFM control structure, which becomes saturated during a symmetrical fault. The current referencing technique compresses the current waveform without any passive components to dissipate the restricted energy during the fault, leading to distortions in the natural response of the signal. When the FRT scheme is involved, THD is reduced, as with traditional FRT, and its values are 10.2% and 11.6% for current and voltage, respectively, as depicted by Figure 9. However, with the proposed adoptive FRT scheme, the quality of the output AC signals is improved to a great extent, as depicted in Figure 10. The percentage of distortion in THD is limited to 2.54% and 2.15% for current and voltage, respectively, with the adoptive FRT scheme because the contribution of the harmonic distortions due to spikes in fault recovery are also eliminated by the spikes limiter. Hence, the FFT analysis for the proposed scheme provides low THD distortions, and low THD means high efficiency.

4.3. Investigation of Proposed Scheme in Grid-Following (GFL) Mode

The proposed FRT scheme is designed specifically for the mitigation of severe fault clearing spikes of grid-forming inverters. However, to authenticate its credibility in different environments, an additional grid-following model is investigated. A 100 kW built-in detailed model of a three-phase grid-connected PV system operating in grid-following mode is employed, which is implemented in the National Renewable Energy Laboratory (NREL) which is the standard test model for researchers [41]. The system is comprised of a PV array, a DC to DC boost converter, and a VSI and L-C-L filter to deliver PV-generated power to the utility-grid.

A three-phase symmetrical fault is applied at the PCC of the grid-connected PV system for 150 ms, and the response of the fundamental electrical variables, such as grid power, voltage, current, and DC link voltage, are evaluated. The behavior of the current during the fault time is effectively optimized with the adoptive FRT scheme in terms of magnitude and ripples without compromising high magnitude fault recovery surges. Although the conventional FRT scheme gives an optimal response during fault time, it is compromised during the fault clearing surges due to the lake of spikes mitigation circuitry, as shown in Figure 11a. The corresponding voltage response in Figure 11b also shows that the voltage sag from zero is enhanced to an acceptable limit with proposed scheme as compared to the conventional method.

Furthermore, the grid power is restored to the nominal value of 100 kW with both FRT schemes, but the efficiency of the proposed FRT method is authenticated during the fault clearing time. Considering the DC link voltage, the symmetrical fault at the grid side directly affects the DC side because the DC link voltage acts as a current source in grid-following mode. Therefore, the severe output response of the DC link voltage is optimized with the proposed adoptive FRT scheme to near the nominal value of 500 V, with smooth behavior after fault clearance, as shown by Figure 12. The smooth and optimal response just after fault clearance authenticates the transient stability of the proposed scheme.

5. Conclusions

The designed adoptive FRT scheme presented in this paper is effectively implemented over the three-bus test system of grid-forming IBRs for the optimization of electrical parameters during large disturbances. The proposed schemes is adopted by cascading two electronic-based circuitries to protect the sensitive switches of the IBRs from overcurrent and high fault switching spikes. Moreover, the system is protected from the instability caused by the loss of the windup characteristics of the PI controller during fault recovery of symmetrical faults using the adoptive FRT scheme. The optimal and robust response of the adoptive FRT scheme is authenticated through comparison with the repeatedly used PRFCL as an FRT scheme. Additionally, the quality of the waveforms and their deviation from nominal values is not compromised by the insertion of the proposed FRT scheme, as verified by THD and the performance indices, respectively.

In the near future, the study will be expanded by the implementation of robust control schemes, including feedback linearization, and adoptive SMC, and a fuzzy-neural network will be analyzed in coordination with the adoptive FRT scheme. Additionally, the optimal simulation response and quality of the electrical variables of the proposed adoptive FRT scheme will be experimentally validated through DSPACE or TMS320F28335 DSP boards using a real-time hardware test setting.